FinFET transistor structure: Question bank — Hardware deep dive

Definition

Symbols used on this page (build these before touching a formula):

$ε_{s i}$ — the permittivity of silicon: how strongly the silicon body lets an electric field pass through it. Bigger $ε_{s i}$ = field spreads more easily through the fin.
$ε_{o x}$ — the permittivity of the gate oxide: the same property for the thin insulator between gate and fin.
$t_{s i}$ — the silicon body thickness (for a fin, its width $W_{f in}$ ): how far across the channel is, from one gated surface to the other.
$t_{o x}$ — the gate-oxide thickness: how far the gate sits from the silicon.
$α$ — the number of gated surfaces controlling the channel: $α = 1$ for a flat planar gate, $α \approx 3$ for a three-sided FinFET, $α = 4$ for gate-all-around. It is a count of controlling faces, not an amount of material. Look at the cross-section below — count the gate edges hugging the fin.

If any symbol still feels shaky, re-read the FinFET transistor structure parent note first.

True or false — justify

Every item is either true or false. Say which, and — more important — say why in terms of $λ$ , $W_{e f f}$ , or gate control.

A FinFET is fundamentally a new kind of transistor with different physics from a MOSFET.

False — it is still a MOSFET (a gate modulating a channel via the field effect); only the geometry changed from flat to a 3D fin wrapped by the gate on three sides. Same physics, better electrostatics.

Making the fin thinner (smaller

W_{f in}

) improves short-channel immunity.

True —

W_{f in}

plays the role of the body thickness

t_{s i}

λ

, and

λ

shrinks as

t_{s i}

shrinks. A thinner fin lets the gate control the whole cross-section, so the drain can't sneak in.

A tall fin (

H_{f in} ≫ W_{f in}

) delivers more drive current per drawn footprint than a planar device of the same footprint.

True — because current flows on both sidewalls plus the top,

W_{e f f} = 2 H_{f in} + W_{f in}

exceeds the fin's footprint once

H_{f in}

is large. (The advantage comes entirely from height; a short fin with tiny

H_{f in}

would not beat planar, which is why real fins are made tall.)

Adding more gates (

α

from 1 to 3) increases the amount of silicon in the channel.

False —

α

counts gated surfaces, not silicon volume. More gates means the same fin is controlled from more sides, which lowers

λ

; it adds gate/oxide coverage, not channel material.

A planar MOSFET can always be shrunk to the same

L_{g}

as a FinFET if you just thin its oxide.

False — thinning

t_{o x}

helps both devices equally, but the planar device is stuck at

α = 1

while the FinFET has

α \approx 3

. That

3

head start on

λ

can't be recovered by oxide alone (and

t_{o x}

has a hard floor from gate leakage).

You can achieve any transistor width in a FinFET by choosing

H_{f in}

freely at layout time.

False —

H_{f in}

is fixed by the fabrication process for the whole chip, not chosen per transistor. Designers only choose the number of fins

N

, so width comes in quantized steps of

2 H_{f in} + W_{f in}

Halving

λ

lets you roughly halve the minimum gate length.

True — the rule

L_{g} ≳ 5 - 6 λ

is linear in

λ

, so cutting

λ

in half cuts the allowed

L_{g}

in half, enabling denser chips.

Gate-All-Around transistors are a step backward from FinFETs.

False — GAA wraps the channel on all four sides, pushing

α \to 4

, which lowers

λ

further than the FinFET's

α \approx 3

. It's the next step forward, taken when even three-sided control isn't enough.

Spot the error

Each statement contains one flawed step. Name it and correct it.

"To boost current, a designer widens each fin, since wider means more current like in a planar device."

The error is treating

W_{f in}

as "the width." In a FinFET the height supplies width (

W_{e f f} \approx 2 H_{f in}

); a wide fin raises

t_{s i}

λ

, worsening short-channel leakage. Correct move: keep fins thin, add taller fins or more fins.

"Since

λ = ε_{s i} t_{s i} t_{o x} / (α ε_{o x})

, using a high-k gate dielectric raises

ε_{o x}

and therefore raises

λ

, which is bad."

The sign of the effect is right (larger

ε_{o x}

lowers

λ

, since it sits in the denominator — good, not bad), but the framing is wrong: high-k is used precisely to get strong coupling with a physically thicker layer that leaks less. It helps.

"A circuit needs

W_{e f f} = 300

nm and one fin gives 87 nm, so we use exactly

300/87 = 3.45

fins."

You cannot build a fractional fin. Width is quantized, so you take

⌈ 3.45 ⌉ = 4

fins, giving

W_{e f f} = 348

nm — a deliberate slight overshoot.

"The natural-length derivation assumes a linear vertical potential, which is why

λ

appears."

The assumption is a parabolic (quadratic) vertical potential across the body, not linear. Integrating Poisson's equation with that parabolic profile collapses the 2D problem to the 1D equation whose coefficient is

1/ λ^{2}

"FinFETs fixed short-channel effects by making the channel longer."

They did the opposite — they let channels stay short while restoring control. The fix is geometric (three-sided gate lowering

λ

), not lengthening the channel.

"Because current flows on three surfaces,

W_{e f f} = 3 W_{f in}

The three surfaces are two sidewalls (each of height

H_{f in}

) plus one top (of width

W_{f in}

), so

W_{e f f} = 2 H_{f in} + W_{f in}

, not

3 W_{f in}

. The sidewalls scale with height, not width.

"Using a high-k dielectric means the oxide is physically thinner, which is how it improves coupling."

Backwards — a high-k stack is physically thicker yet electrically behaves like a thin

SiO_{2}

layer. What matters is the equivalent oxide thickness

EOT = t_{hi g h - k} \cdot (ε_{S i O_{2}} / ε_{hi g h - k})

: high

ε

lets a thick film have a small EOT, giving strong coupling and low tunnelling.

Why questions

Answer with a mechanism, not a restatement.

Why does the drain "steal" control of the channel in a short planar device but far less in a FinFET?

In a planar device the gate touches only the top, so as

L_{g}

approaches the channel's control length

λ

, the drain's field reaches across (DIBL). The FinFET's three-sided gate lowers

λ

(via

α \approx 3

), so the same short

L_{g}

is still many

λ

long and the drain's reach is choked off.

Why does the number of gates appear in the denominator of

λ

More gated surfaces means the boundary conditions clamp the channel potential from more directions, so the gate's influence decays over a shorter distance. Mathematically the surface terms add when integrating Poisson's equation, multiplying the coupling by

α

and shrinking

λ \propto 1/ α

Why are tall, thin fins the ideal, rather than short, wide ones?

Tall gives large

W_{e f f} \approx 2 H_{f in}

(more current per footprint), and thin gives small

t_{s i}

(small

λ

, good electrostatics). A short wide fin loses on both counts. Thinness and height fight leakage and boost current at once.

Why is a FinFET's width called "quantized" while a planar width is continuous?

Planar width is a drawn dimension you can set to any value. FinFET width is built from whole fins of fixed cross-section, so total width jumps in discrete units of

2 H_{f in} + W_{f in}

— there's no half-fin.

Why does thinning the gate oxide

t_{o x}

help, and why can't we thin it without limit?

Thinner oxide (smaller EOT) strengthens gate-to-channel coupling, lowering

λ

. But below a couple of nanometers physical thickness, electrons tunnel straight through (gate leakage), which is exactly why high-k dielectrics let you keep small EOT at a safe physical thickness.

Why did the industry need FinFETs to keep Moore's Law going even though planar scaling once worked fine?

Planar scaling relied on Dennard Scaling, where shrinking dimensions and voltages kept power density flat. Once

L_{g}

dropped near

λ

, leakage broke that bargain; the FinFET's lower

λ

restored gate control so shrinking could continue.

Why does doubling

H_{f in}

roughly double drive current but not change

λ

Drive current scales with

W_{e f f} \approx 2 H_{f in}

, so it doubles. But

λ

depends on

t_{s i}

(the fin width) and

t_{o x}

, not on the fin height — so making the fin taller adds current without touching the electrostatics.

Edge cases

Boundary and degenerate scenarios — where naive intuition breaks.

H_{f in} \to 0

(a fin with no height), what does the FinFET become?

W_{e f f} = 2 H_{f in} + W_{f in} \to W_{f in}

: the sidewalls vanish and only the top conducts. Electrically it degenerates toward a narrow single-gate planar strip — you've lost the FinFET's advantage.

If you set

α = 1

in the natural-length formula, what device are you describing?

A single-gate device — the planar MOSFET. Setting

α = 1

removes the multi-gate benefit, so

λ

is at its largest and short-channel immunity is worst.

What happens to

λ

α \to \infty

(imagining infinitely many gates)?

λ \propto 1/ α \to 0

, meaning perfect gate control at any gate length. Real devices stop at

α = 4

(Gate-All-Around) because a channel has only so many surfaces to wrap.

For a needed width that is an exact multiple of one fin's

W_{e f f}

, is there still overshoot?

No — if

300/ W_{e f f}

were a whole number,

⌈ \cdot ⌉

returns it unchanged and there's zero overshoot. Overshoot only appears when the required width isn't a clean multiple of a fin.

If two designs have the same

λ

but different

L_{g}

, which switches off more cleanly?

The one with the larger

L_{g}

, because short-channel effects depend on the ratio

L_{g} / λ

. Same

λ

, longer channel means more gate margin and a sharper OFF state.

What limits how thin

W_{f in}

(and thus

t_{s i}

) can go, given that thinner is electrostatically better?

Fabrication — etching an ultra-thin fin without variation or roughness is hard, and quantum/surface-scattering effects degrade mobility. So there's a practical floor even though the physics wants

t_{s i} \to 0

If a fin is made both very thin and very short, what have you effectively built?

A tiny, low-current device with good electrostatics (small

λ

) but almost no drive (

W_{e f f}

tiny). You'd need many such fins in parallel to carry useful current — trading area for control.

Recall

Fresh one-line summary — reason it out from the exponential decay picture, don't recite. A single quantity, when made small, simultaneously buys shorter allowed $L_{g}$ and cleaner OFF states — name it and say why. ::: The natural length $λ$ : the drain's field decays as $e^{- y / λ}$ , so a smaller $λ$ means the drain's influence dies out over a shorter distance, letting $L_{g}$ (which must exceed $\approx 5 λ$ ) shrink while the source barrier stays protected.

Prerequisites revisited: Planar MOSFET · Short-Channel Effects · DIBL · Poisson's Equation in MOS Electrostatics · Gate Oxide and High-k Dielectrics · Gate-All-Around Transistor · Moore's Law · Dennard Scaling