Gate-all-around (GAA) nanosheet transistors

WHY does GAA exist? (The problem it solves)

Electrostatic control ladder (WHAT gets better with each step):

Device	Gate sides	Best control
Planar	1	worst
FinFET (tri-gate)	3	good
GAA nanosheet	4 (all-around)	best

WHAT is a nanosheet? (Definitions)

HOW is it built? (The key process trick)

Process flow (WHY at each step):

Epitaxy: grow alternating Si / SiGe layers. Why: SiGe etches ~100× faster than Si in the right chemistry → a built-in "remove me" marker.
Fin patterning: etch the stack into narrow fins. Why: defines sheet width $W_{ns}$ .
Dummy gate + spacers: place a temporary gate. Why: protects channel region; gate-last flow.
Source/drain recess + epi: grow doped S/D. Why: inject carriers into all sheets.
Channel release: selectively etch the SiGe → floating Si nanosheets. Why: this is what makes it "all-around."
Gate stack fill: deposit high- $k$ dielectric + metal by ALD (atomic layer deposition) so it conformally coats every surface, wrapping each sheet. Why: ALD is atom-thin and conformal — reaches into the narrow gaps.

Figure — Gate-all-around (GAA) nanosheet transistors

The physics: WHY all-around control beats 3-sided

Formula Deriving

$\lambda$ for a gate-all-around cylinder Start from the 2-D Poisson equation in the channel and assume a parabolic potential across the channel body (the standard scaling-theory ansatz). Solving Laplace/Poisson with the boundary that the gate fixes the potential on the entire perimeter gives, for a surrounding-gate wire of diameter $d_{si}$ : $\boxed{\;\lambda_{GAA} = \sqrt{\dfrac{2\,\varepsilon_{si}\,t_{ox}\,d_{si} + \varepsilon_{ox}\,d_{si}^{2}}{16\,\varepsilon_{ox}}}\;}$ HOW to read it: compared to a single-gate device $\lambda_{single}=\sqrt{\frac{\varepsilon_{si}}{\varepsilon_{ox}}t_{ox}\,t_{si}},$ the GAA form has an extra 1/4 style factor coming from control on all sides → smaller $\lambda$ → shorter $L_g$ allowed. Why smaller: each extra gate side adds a term to the denominator that shrinks the penetration depth.

Take-away: More gate coverage → smaller $\lambda$ → drain field is screened → less DIBL, steeper subthreshold slope, lower leakage.

Worked examples

Common mistakes (Steel-manned)

Flashcards

How many sides does a GAA gate control vs a FinFET gate?

GAA controls all 4 sides (surrounding); FinFET controls 3 sides.

What is the sacrificial material etched to release Si nanosheets?

SiGe (etched selectively, leaving the Si sheets suspended).

Give the effective width of one nanosheet wrapped on all sides.

W_{eff}=2(W_{ns}+T_{ns})

Why does stacking nanosheets increase current without more area?

Each sheet adds

\approx 2(W_{ns}+T_{ns})

of gate-controlled width in the same footprint, so total

W_{eff}=N\cdot2(W_{ns}+T_{ns})

What device parameter measures drain-field penetration, and is small good or bad?

The natural/screening length

\lambda

; small

\lambda

is good (drain can't reach across the channel).

Rule of thumb linking

L_g

and

\lambda

Need

L_g \gtrsim 5\lambda

for good short-channel control.

Which deposition method conformally fills the gate around suspended sheets, and why?

ALD — self-limiting and conformal, so it coats every released surface.

What tunable knob does GAA give that FinFET cannot?

Sheet width

W_{ns}

(continuously trade drive current vs power/control), instead of quantized fin height.

Name two short-channel benefits of all-around control.

Lower DIBL and steeper (nearer-ideal) subthreshold slope ⇒ less leakage.

Why can't you just skip SiGe and float pure Si sheets?

Nothing would hold the sheets during fab; SiGe provides the sacrificial spacer that's later removed to suspend the Si.

Recall Feynman: explain to a 12-year-old

Imagine a garden hose (the electron path) and your hand squeezing it to stop the water. In an old design your hand pressed only one side and water still leaked. FinFET squeezed three sides. The new GAA design makes tiny flat ribbons of silicon floating in space, and the "hand" (the gate) wraps all the way around each ribbon — like closing your whole fist. Best squeeze = least leak. And they stack several ribbons on top of each other, so you get more water flow in the same small spot. The clever building trick: they stack silicon and a helper material (SiGe), then dissolve only the helper so the silicon ribbons hang free, ready to be wrapped.

Connections

FinFET (tri-gate) transistors — the predecessor with 3-sided control.
Short-channel effects and DIBL — the problem GAA fights via smaller $\lambda$ .
Atomic Layer Deposition (ALD) — how the wrap-around gate is filled.
Epitaxy and SiGe superlattices — how the sheet stack is grown.
High-k metal gate stack — the dielectric+metal that surrounds each sheet.
Subthreshold slope and gate electrostatics — the metric that improves.
CFET (complementary FET) — the next step: stacking n over p GAA devices.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, transistor basically ek electron ka nal (tap) hai, aur gate us nal pe tumhara haath hai. Jitne zyada side se tum channel ko pakdoge, utna behtar control — matlab jab "off" bolo to sach me off, koi leakage nahi. Purana planar design sirf 1 side pakadta tha, FinFET 3 side (top + do walls), lekin GAA nanosheet poore 4 sides ko wrap karta hai. Isiliye GAA ka gate drain ke against tug-of-war jeet jata hai, aur short-channel effects (leakage, DIBL) kam ho jaate hain.

Banane ka jugaad kya hai? Tum Si aur SiGe ki alternating layers grow karte ho (superlattice). Fir SiGe ko selectively etch kar dete ho — Si ki patli sheets hawa me suspend ho jaati hain. Ab ALD se high-k dielectric aur metal daal ke har sheet ke chaaro taraf gate bhar dete ho. Yaad rakho: Si nahi, SiGe hatate hain — yeh sabse common galti hai.

Physics side pe ek number hai $\lambda$ (natural length) — yeh batata hai drain ka field channel me kitna ghusta hai. Chhota $\lambda$ = accha, kyunki drain reach nahi kar pata. All-around control $\lambda$ ko chhota karta hai, isliye tum gate length aur chhoti rakh sakte ho ( $L_g \gtrsim 5\lambda$ ) bina leakage ke — matlab denser aur faster chip.

Aur ek bada fayda: sheets ko stack karte ho, to same footprint (jagah) me current multiply ho jaata hai. Har sheet ka $W_{eff}=2(W_{ns}+T_{ns})$ , aur N sheets ka total N guna. Plus, tum sheet width ko tune kar sakte ho — high performance chahiye to chaudi, low power chahiye to patli. FinFET me yeh flexibility nahi thi. Isiliye 3nm aur uske aage GAA industry ka standard ban raha hai.

WHY does GAA exist? (The problem it solves)

WHAT is a nanosheet? (Definitions)

HOW is it built? (The key process trick)

The physics: WHY all-around control beats 3-sided

Worked examples

Common mistakes (Steel-manned)

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Semiconductor Fabrication

Connections