Gate-all-around (GAA) nanosheet transistors: Worked examples

See the parent: Gate-all-around (GAA) nanosheet transistors.

The scenario matrix

Every worked example below is tagged with the cell of this table it covers. Together they fill every cell.

Cell	Case class	What makes it special	Example
A	Ordinary width	plain numbers, one sheet	Ex 1
B	Stacking ( $N$ sheets)	multiply by $N$ , same footprint	Ex 2
C	Degenerate: square ( $W_{n s} = T_{n s}$ )	sheet → nanowire limit	Ex 3
D	Zero / limiting ( $T_{n s} \to 0$ )	thinnest possible sheet	Ex 4
E	Cross-over / tie	GAA $W_{e f f}$ = FinFET $W_{e f f}$	Ex 5
F	Screening length $λ$	plug into the $λ$ formula, all signs positive	Ex 6
G	Word problem (design target)	"how many sheets for a current spec?"	Ex 7
H	Exam twist / trap	wide-sheet trade-off, "more is worse"	Ex 8

Worked examples

Worked example Example 1 — Ordinary single sheet

(Cell A) A nanosheet has width $W_{n s} = 40 nm$ and thickness $T_{n s} = 5 nm$ . Find $W_{e f f}$ for one sheet.

Forecast: guess — will it be near 40, near 80, or near 90 nm?

Identify the perimeter the gate wraps. Why this step? GAA control is all-around, so the gate touches all four edges of the rectangle — the width the transistor "feels" is the whole perimeter, not just the top.
Two long sides: $2 W_{n s} = 2 \times 40 = 80 nm$ . Why this step? These are the wide top and bottom faces.
Two thin edges: $2 T_{n s} = 2 \times 5 = 10 nm$ . Why this step? These are the two narrow vertical sidewalls.
Add them: $W_{e f f} = 80 + 10 = 90 nm$ . Why this step? Perimeter $= 2 (W_{n s} + T_{n s})$ .

Verify: $2 (40 + 5) = 2 (45) = 90 nm$ . Units: nm + nm inside, ×2 → nm. ✅ Bigger than 40 (we added the edges), smaller than $4 \times 40$ — sane.

Figure — Gate-all-around (GAA) nanosheet transistors

Worked example Example 3 — Degenerate: the square cross-section (nanowire limit)

(Cell C) Let the sheet shrink until width equals thickness: $W_{n s} = T_{n s} = 8 nm$ . Find $W_{e f f}$ and say what device this has become.

Forecast: a "wide slab" formula fed a square — does it still make sense?

Plug equal values: $W_{e f f} = 2 (8 + 8) = 32 nm$ . Why this step? The perimeter formula doesn't care that the shape is square — it's still just perimeter.
Recognise the shape: a square (nearly circular) cross-section is a nanowire, not a nanosheet. Why this step? The parent definition says thin wire = nanowire; the formula degrades gracefully to it.
Cross-check with a circle of equal area diameter: a square side $8$ has perimeter $32$ ; a circle of diameter $8$ has perimeter $π \cdot 8 \approx 25.1 nm$ . Why this step? Confirms the square case sits sensibly near the round-wire case.

Verify: $2 (8 + 8) = 32 nm$ . Square perimeter $= 4 \times 8 = 32$ ✅ (matches). The formula stays valid at the sheet→wire boundary.

Worked example Example 4 — Zero / limiting: the impossibly thin sheet

(Cell D) Take $W_{n s} = 40 nm$ and let $T_{n s} \to 0$ . What does $W_{e f f}$ approach, and what does that mean physically?

Forecast: as thickness vanishes, does width vanish too?

Substitute the limit: $W_{e f f} = 2 (40 + 0) = 80 nm$ . Why this step? Setting $T_{n s} = 0$ removes the two edge contributions.
Interpret: only the top + bottom faces survive; the gate wraps a sheet of zero height. Why this step? $2 T_{n s} \to 0$ means the vertical sidewalls disappear — the "all-around" collapses to "top+bottom".
Physical caution: a truly zero-thickness sheet has no body to conduct — this is a math limit, not a fabricable device. Why this step? Case coverage must flag when the number is real but the device isn't.

Verify: $lim_{T_{n s} \to 0} 2 (40 + T_{n s}) = 80 nm$ . Sanity: thinner sheet ⇒ smaller $W_{e f f}$ (we removed $2 T_{n s}$ ), monotone and finite. ✅

Worked example Example 6 — Screening length

$λ$ , all inputs positive (Cell F) For a surrounding-gate wire use $λ_{G AA} = \frac{2 ε _{s i} t _{o x} d _{s i} + ε _{o x} d _{s i}^{2}}{16 ε _{o x}} .$ Take $ε_{s i} = 11.7$ , $ε_{o x} = 3.9$ , $t_{o x} = 1 nm$ , $d_{s i} = 8 nm$ (all $ε$ are relative, so unitless; lengths in nm). Find $λ_{G AA}$ .

Forecast: will $λ$ land near 3–4 nm (the "good" range from the parent)?

Numerator term 1: $2 ε_{s i} t_{o x} d_{s i} = 2 \times 11.7 \times 1 \times 8 = 187.2$ . Why this step? This term is the drain field leaking through the oxide over the body.
Numerator term 2: $ε_{o x} d_{s i}^{2} = 3.9 \times 64 = 249.6$ . Why this step? This term is the field spreading inside the silicon body.
Numerator sum $= 187.2 + 249.6 = 436.8$ ; denominator $= 16 \times 3.9 = 62.4$ . Why this step? The $16$ is the "all-around" bonus — it shrinks $λ$ versus single-gate.
$λ = 436.8/62.4 = 7.0 \approx 2.646 nm$ . Why this step? Take the square root; units are $nm^{2} = nm$ .
Rule of thumb: $L_{g} \geq 5 λ \approx 13.2 nm$ . Why this step? Turns $λ$ into a minimum safe gate length.

Verify: $436.8/62.4 = 7.0$ , $7.0 = 2.6458 nm$ , in the "good" (small) band. Units under the root: (nm·nm inside) / (unitless) → nm² → nm. ✅ See Short-channel effects and DIBL.

Worked example Example 7 — Word problem: hitting a current target

(Cell G) A logic cell needs an on-current that scales with total gate width. The spec says $W_{e f f, t o t a l} \geq 200 nm$ . Your process gives sheets of $W_{n s} = 45 nm$ , $T_{n s} = 5 nm$ . How many sheets must you stack?

Forecast: two sheets, three, or four?

Per-sheet width: $2 (45 + 5) = 100 nm$ . Why this step? Perimeter of one sheet — the width unit we stack.
Required count: $N \geq 200/100 = 2$ . Why this step? Total width is $N \times 100$ ; solve for $N$ .
Exactly $N = 2$ meets the spec at $200 nm$ (no rounding needed). Why this step? $200$ is an exact multiple of $100$ , so we land on the boundary.
Footprint check: stacking is vertical → floor area unchanged. Why this step? Confirms we met the current spec without spending area — see Epitaxy and SiGe superlattices for how the stack is grown.

Verify: $2 \times 2 (45 + 5) = 2 \times 100 = 200 nm \geq 200$ . ✅ $N = 1$ gives only $100 < 200$ (fails), so 2 is minimal.

Worked example Example 8 — Exam twist / trap: does a wider sheet always win?

(Cell H) Design A: one sheet $W_{n s} = 60$ , $T_{n s} = 6$ . Design B: one sheet $W_{n s} = 30$ , $T_{n s} = 6$ . Compute both $W_{e f f}$ . Trap: which one has better short-channel control, and why is the bigger $W_{e f f}$ not automatically "better"?

Forecast: the wide one has more width — is it the better transistor?

Design A: $2 (60 + 6) = 132 nm$ . Why this step? Perimeter of the wide sheet.
Design B: $2 (30 + 6) = 72 nm$ . Why this step? Perimeter of the narrow sheet.
The wide sheet A has more drive current (bigger $W_{e f f}$ ). Why this step? On-current $\propto W_{e f f}$ .
But the middle of a very wide sheet is far from the two thin sidewall gates, so those sidewalls control it less — electrostatics weaken and it drifts toward planar behaviour (worse control). Why this step? This is the drive-current-vs-control trade-off the parent flagged; more width ≠ strictly better.

Verify: $2 (60 + 6) = 132$ , $2 (30 + 6) = 72$ , and $132 > 72$ (A is wider). The trap is qualitative: bigger $W_{e f f}$ but weaker per-unit-width control. See Subthreshold slope and gate electrostatics. ✅

Recall

Recall Which cell did each formula stress?

How do you get one sheet's width? ::: perimeter $2 (W_{n s} + T_{n s})$ (Cell A). How do you get a stack's width? ::: multiply by $N$ : $N \cdot 2 (W_{n s} + T_{n s})$ (Cell B). What happens to the formula for a square (wire) cross-section? ::: it still equals the perimeter, $2 (W + T) = 4 W$ when $W = T$ (Cell C). Is bigger $W_{e f f}$ always better? ::: No — wide sheets lose short-channel control (Cell H trade-off). Small or large $λ$ is good? ::: Small — drain field can't reach across (Cell F).