Question bank — Gate-all-around (GAA) nanosheet transistors

TRUE — the sheet is released (suspended), so the gate metal wraps top, bottom, and both edges; that full wrap is the entire point of "gate-all-around."

FALSE — a FinFET grips only 3 sides (top and two walls); the fin bottom stays anchored to the substrate, so the drain can still reach through that unguarded face. See FinFET (tri-gate) transistors.

FALSE — the SiGe is sacrificial and etched out; the Si sheets are kept as channels. Reversing this is the classic exam trap.

TRUE — small $\lambda$ means the drain field penetrates less, so the gate wins the tug-of-war; this is why the rule $L_g\gtrsim 5\lambda$ lets a smaller $\lambda$ permit a shorter gate.

FALSE — the sheets stack vertically in the same floor area, so current rises while footprint stays fixed; that "more current per unit area" is GAA's headline win.

FALSE — wider sheets raise drive current but weaken the electrostatic grip at the sheet's middle (far from the edges), degrading short-channel control; it's a trade-off, not a free win.

FALSE — you must coat underneath a suspended sheet in a narrow gap; only self-limiting, conformal Atomic Layer Deposition (ALD) reaches every surface uniformly.

TRUE — same all-around gate idea; a nanosheet is a wide thin slab, a nanowire is a narrow thin wire, and both are GAA channels.

The wrong part is "identical" — a FinFET's channel is attached at its base (3-side control), while a GAA channel is released/suspended so the gate closes the 4th side; that extra surface is a genuinely different electrostatic situation, not a rotation.

Backwards — SiGe is removed (it etches ~100× faster in the right chemistry) and Si is the surviving channel. The whole difficulty is finding an etch that spares Si while devouring SiGe.

$\lambda$ measures the drain's reach, not the gate's — big $\lambda$ means the drain penetrates deep and causes leakage, so bigger $\lambda$ is worse.

The dummy gate is temporary — it holds the channel region during processing and is later removed so the real high-k metal gate can be filled in a gate-last flow. See High-k metal gate stack.

Missing the factor 2 — the gate wraps the full perimeter, so you count both long faces and both thin edges: $W_{eff}=2(W_{ns}+T_{ns})$.

"Perfectly" is too strong — GAA reduces DIBL versus FinFET by shrinking $\lambda$, but the drain field is only screened, never fully eliminated; see Short-channel effects and DIBL.

The alternating crystalline stack must be grown by epitaxy so each layer inherits the crystal lattice; a random sputtered film wouldn't form the clean superlattice needed. See Epitaxy and SiGe superlattices.

More gate coverage means tighter electrostatic control, so a small change in gate voltage swings the channel from off to on faster — fewer volts per decade of current. See Subthreshold slope and gate electrostatics.

The gate must coat the underside of a suspended sheet inside a narrow gap; ALD builds one self-limiting atomic layer at a time, so it reaches shadowed surfaces that line-of-sight methods miss.

You set current by choosing $W_{ns}$ (wide = high drive, narrow = low power) at design time, whereas a FinFET's drive is locked to its fixed fin height — you could only add whole fins.

The drain field decays over roughly $\lambda$, so a gate several $\lambda$ long ensures the channel middle is deep in "gate territory" where the drain's exponentially-faded influence is negligible.

Removing the SiGe is exactly what frees the silicon sheet so the gate can wrap the 4th (bottom) side — without it you'd only ever get FinFET-style 3-side control.

A high-k layer lets the gate couple strongly to the channel with a physically thicker film, cutting leakage while keeping tight control — pairing naturally with the conformal ALD fill. See High-k metal gate stack.

It degrades toward planar behaviour — the middle of a very wide sheet sits far from any edge-gate influence, so the top/bottom faces alone must hold control, and DIBL creeps back.

You still get full all-around control and clean switching, but you sacrifice the current-per-area advantage — you're using the same footprint for a single sheet's worth of $W_{eff}$.

The Si sheets thin, roughen, or break, changing $T_{ns}$ and $W_{eff}$ and hurting yield — which is why the etch-chemistry selectivity is the make-or-break step.

$\lambda$ shrinks too — a thinner body leaves the drain field nowhere to sneak through, giving the best short-channel immunity (at the cost of harder fabrication and higher resistance).

No — taller stacks strain the SiGe/Si epitaxy, make the release etch and gate fill harder to reach the innermost gaps, and eventually parasitics and defects cap the useful stack height.

That's the natural next step, the CFET, which stacks complementary transistors vertically for even more density; the all-around release/fill toolkit carries straight over. See CFET (complementary FET).