Gate-all-around (GAA) nanosheet transistors: Foundations

Before we can read a single formula from the parent note, we must earn every symbol in it. This page is a dictionary where each entry has three parts: what it means in plain words, the picture it draws, and why the topic needs it. Read top to bottom — each one leans on the one above.

0. The stage everything sits on

Let's first agree on the physical scene, because every symbol is a measurement on this scene.

Figure — Gate-all-around (GAA) nanosheet transistors

Everything below is a number describing either the bridge's shape or how tightly the gate holds it.

1. Geometry symbols — the shape of the channel

$L_{g}$ — gate length

$W_{n s}$ and $T_{n s}$ — nanosheet width and thickness

$d_{s i}$ and $t_{s i}$ — body diameter / body thickness

2. Counting symbols — sides and sheets

"Number of gate sides" (1, 3, 4)

$N$ — number of stacked sheets

3. The "grip" symbols — effective width and screening length

$W_{e f f}$ — effective width

$W_{e f f}$ depends on how many sides the gate reaches — so every case has its own formula:

Case	Sides gripped	Which edges add up	$W_{e f f}$ per sheet
Planar (1-side)	top only	one long side	$W_{n s}$
Tri-gate / FinFET (3-side)	top + two walls	one long + two short	$W_{n s} + 2 T_{n s}$
GAA (4-side)	all around	two long + two short	$2 (W_{n s} + T_{n s})$

$λ$ — natural / screening length

4. The material symbols — permittivities and oxide thickness

Now the ingredients that appear inside the $λ$ formula.

$ε_{0}$ , $ε_{r}$ (also called $k$ ), and $ε$ — permittivity

Definition Permittivity: absolute vs relative

Permittivity measures a material's willingness to let an electric field pass through it.

$ε_{0}$ = vacuum permittivity, a fixed constant of nature, $ε_{0} \approx 8.85 \times 1 0^{- 12} F/m$ . It is the "baseline" for empty space.
$ε_{r}$ = relative permittivity: a plain dimensionless number saying "how many times more than vacuum." In fabrication circles this same number is written $k$ (the " $k$ " in high-$k$) — so $k \equiv ε_{r}$ , they are two names for one quantity. Silicon has $ε_{r, s i} = k_{s i} \approx 11.7$ ; silicon dioxide $ε_{r, o x} = k_{o x} \approx 3.9$ .
$ε$ = absolute permittivity of the material $= ε_{r} ε_{0} = k ε_{0}$ , measured in $F/m$ .

A subscript names the material: $ε_{s i} = k_{s i} ε_{0}$ = silicon, $ε_{o x} = k_{o x} ε_{0}$ = the gate oxide.

Picture: think of $ε$ (equivalently $k$ ) as how "soft" a material is to field lines — a high- $k$ material lets field lines pass easily.
Why the topic needs it: the fight is "gate field vs drain field." How well each side wins depends on the permittivities of the layers the fields cross. That's why $λ$ contains a ratio $ε_{s i} / ε_{o x} = k_{s i} / k_{o x}$ — and because it's a ratio, the $ε_{0}$ cancels, leaving just the pure $k$ ratio.

$t_{o x}$ — oxide thickness

5. The $λ$ family — one formula per geometry

The parent note promises a device-specific $λ$ . Here is the whole family, one member per number-of-gate-sides, so no case is left to guess. Each comes from the same recipe (below), differing only in how many sides fix the potential.

Formula The three screening lengths

Single-gate (planar, 1 side) — flat slab of thickness $t_{s i}$ : $λ_{s in g l e} = \frac{ε _{s i}}{ε _{o x}} t_{o x} t_{s i}$ Double-gate / tri-gate style (gate on opposite/several faces) — slab of thickness $t_{s i}$ : $λ_{d o u b l e} = \frac{ε _{s i}}{2 ε _{o x}} t_{o x} t_{s i}$ Gate-all-around (4 sides / surrounding) — round wire of diameter $d_{s i}$ : $λ_{G AA} = \frac{2 ε _{s i} t _{o x} d _{s i} + ε _{o x} d _{s i}^{2}}{16 ε _{o x}}$ How to read the pattern: each extra gripped side puts a bigger number in the denominator ( $1 \to 2 \to 16$ style factors) → smaller $λ$ → shorter allowed $L_{g}$ . The GAA form uses $d_{s i}$ (round wire), the single/double forms use $t_{s i}$ (flat slab) — exactly matching the shapes from §1. Notice every version is a ratio of permittivities times lengths, all under a square root, so every one comes out in nm.

Recall Where does the square root and the parabolic-potential recipe come from?

All three formulas are found the same way. The steps, from zero:

Write the field law inside the silicon. The 2-D Poisson equation says the potential $ϕ (x, y)$ curves in proportion to charge; in the lightly-doped channel we can use its charge-free cousin (Laplace's equation) as the leading approximation. In plain words: "how the potential bends left-to-right plus how it bends top-to-bottom must balance."
Guess the shape across the body (the "ansatz"). Across the thin body direction we assume $ϕ$ is a parabola — flat where the gate grips, dipping in the middle. Why a parabola: it is the simplest curve that is symmetric and can match a fixed value at the gripped surface(s); the gate pins the two (or all-around) edges, and a parabola is what you get between two pinned edges.
Apply the boundary condition — this is where "how many sides" enters. The gate fixes the potential on each surface it touches. One touched face (single-gate) vs opposite faces (double) vs the entire perimeter (GAA) changes how much curvature the parabola must supply — and that is precisely the $1$ vs $2$ vs $16$ factor in the denominators.
Collapse to one equation for the along-channel potential. Averaging the parabola turns the 2-D problem into a 1-D equation of the form $\frac{d ^{2} ψ}{d x ^{2}} = \frac{ψ}{λ ^{2}}$ . The constant $λ^{2}$ that pops out is a product of two lengths (across the oxide $t_{o x}$ and across the body $t_{s i}$ or $d_{s i}$ ) weighted by the permittivity ratio.
Take the root. Because $λ^{2}$ came out as (length $\times$ length), the distance $λ$ is its square root — just as the side of a square is the root of its area. That is the whole origin of the .

Why does the double-gate get a factor 2 vs single-gate? ::: The gate grips two opposite faces instead of one, so the parabola is pinned at both ends and needs half the penetration — the extra pinned face divides $λ^{2}$ by 2. Why does the GAA (round-wire) formula look different, with $d_{s i}^{2}$ ? ::: It is derived in cylindrical coordinates (a round wire of diameter $d_{s i}$ ), not a flat slab, so the geometry produces a $d_{s i}$ and a $d_{s i}^{2}$ term and the surrounding-gate factor 16 in the denominator.

How these foundations feed the topic

The left branch is geometry and grip (what we measure); the right branch is process (how we physically make the 4-side grip possible). They meet at the finished GAA device.

6. The process symbols — the words on the build recipe

These aren't in a formula, but the parent note uses them as if defined. Here they are.

Equipment checklist

Cover the right side and test yourself — you're ready for the parent note when every one is instant.

What does the acronym GAA expand to?

Gate-All-Around — the gate conductor wraps the channel on all sides.

Units of

L_{g}

W_{n s}

T_{n s}

t_{o x}

λ

Nanometres (nm), since

1 nm = 1 0^{- 9} m

L_{g}

in one sentence

The channel length under the gate, measured source-to-drain; small

L_{g}

is dense but leaky.

W_{n s}

T_{n s}

Width and thickness of the sheet's cross-section rectangle — the wide dimension vs the thin dimension.

W_{e f f}

for planar / tri-gate / GAA (1 sheet)

W_{n s}

W_{n s} + 2 T_{n s}

2 (W_{n s} + T_{n s})

— add only the edges the gate actually touches.

Effect of stacking

N

GAA sheets on

W_{e f f}

Multiplies it:

W_{e f f, t o t a l} = N \cdot 2 (W_{n s} + T_{n s})

in the same footprint.

What

λ

measures and whether small is good

How far the drain field leaks into the channel; small

λ

is good; it is device-specific (

λ_{s in g l e}

λ_{d o u b l e}

λ_{G AA}

Which body dimension does

λ_{G AA}

use, and which does

λ_{s in g l e}

use?

λ_{G AA}

uses

d_{s i}

(round wire);

λ_{s in g l e}

uses

t_{s i}

(flat slab).

The rule linking

L_{g}

and

λ

L_{g} ≳ 5 λ

for good short-channel control.

k

and

ε_{r}

— how are they related?

They are the same quantity;

k \equiv ε_{r}

, the relative permittivity (dielectric constant), and

ε = k ε_{0}

Absolute vs vacuum permittivity

ε = k ε_{0}

;

ε_{0} \approx 8.85 \times 1 0^{- 12}

F/m is vacuum permittivity.

Why thin

t_{o x}

helps

The gate sits closer to the channel, tighter grip, smaller

λ

Which material is sacrificial in the superlattice

SiGe is etched away; Si sheets are kept.

Why ALD (not any deposition) fills the gate

It coats one atomic layer at a time, conformally reaching the hidden top/bottom/sides of a released sheet.

Number of gate sides: planar / FinFET / GAA

1 / 3 / 4.