Gate-all-around (GAA) nanosheet transistors: Foundations

4.3.20 · D1 · Hardware › Semiconductor Fabrication › Gate-all-around (GAA) nanosheet transistors

Pehle se parent note ka ek bhi formula padhne ke liye, humein uske har symbol ko samajhna hoga. Yeh page ek dictionary hai jahan har entry ke teen parts hain: plain words mein kya matlab hai, woh kya picture banaata hai, aur topic ko iska zaroorat kyun hai. Upar se neeche padho — har ek upar waale pe lean karta hai.

0. Woh stage jis par sab kuch baitha hai

Pehle physical scene pe agree karte hain, kyunki har symbol is scene pe ek measurement hai.

Figure — Gate-all-around (GAA) nanosheet transistors

Neeche sab kuch ya toh pul ki shape describe karta hai ya gate use kitni tightly pakdta hai, woh number hai.

1. Geometry symbols — channel ki shape

$L_{g}$ — gate length

$W_{n s}$ aur $T_{n s}$ — nanosheet width aur thickness

$d_{s i}$ aur $t_{s i}$ — body diameter / body thickness

2. Counting symbols — sides aur sheets

"Number of gate sides" (1, 3, 4)

$N$ — stacked sheets ki sankhya

3. "Grip" symbols — effective width aur screening length

$W_{e f f}$ — effective width

$W_{e f f}$ depend karta hai gate kitne sides tak pahunchti hai — toh har case ka apna formula hai:

Case	Sides gripped	Kaunse edges add hote hain	$W_{e f f}$ per sheet
Planar (1-side)	sirf top	ek long side	$W_{n s}$
Tri-gate / FinFET (3-side)	top + do walls	ek long + do short	$W_{n s} + 2 T_{n s}$
GAA (4-side)	poori taraf se	do long + do short	$2 (W_{n s} + T_{n s})$

$λ$ — natural / screening length

Definition

$λ$ (natural length), nm mein Woh doori jitni drain ki electric field channel mein reach kar sakti hai gate ke screen karne se pehle. Chhota $λ$ = accha (drain across nahin pahunch sakta), bada $λ$ = bura. Kyunki wrapping ki maatra screening ko change karti hai, $λ$ device-specific hai: hum $λ_{s in g l e}$ , $λ_{t r i}$ , $λ_{G AA}$ , etc. likhte hain — bare $λ$ ka matlab sirf hai "jis bhi device ki baat ho rahi hai uski natural length."

Picture: figure s04 drain field ko arrows ke roop mein dikhata hai jo daayein se leak ho rahe hain; $λ$ woh doori hai kitni door arrows penetrate karte hain gate ke bandh karne se pehle.
Topic ko iska zaroorat kyun: yeh vague idea "gate channel ko acchi tarah control karta hai" ko ek number mein badal deta hai jise tum compare kar sako. Rule of thumb $L_{g} ≳ 5 λ$ batata hai transistor kitna chhota banaya ja sakta hai.

4. Material symbols — permittivities aur oxide thickness

Ab woh ingredients jo $λ$ formula ke andar aate hain.

$ε_{0}$ , $ε_{r}$ (jo $k$ bhi kehte hain), aur $ε$ — permittivity

Definition Permittivity: absolute vs relative

Permittivity kisi material ki willingness measure karta hai ki electric field use pass karne de.

$ε_{0}$ = vacuum permittivity, nature ka ek fixed constant, $ε_{0} \approx 8.85 \times 1 0^{- 12} F/m$ . Yeh empty space ke liye "baseline" hai.
$ε_{r}$ = relative permittivity: ek plain dimensionless number jo kehta hai "vacuum se kitne guna zyada." Fabrication circles mein yahi number $k$ likha jaata hai (woh " $k$ " high-$k$ mein) — toh $k \equiv ε_{r}$ , yeh ek quantity ke do naam hain. Silicon ka $ε_{r, s i} = k_{s i} \approx 11.7$ hai; silicon dioxide ka $ε_{r, o x} = k_{o x} \approx 3.9$ .
$ε$ = material ki absolute permittivity $= ε_{r} ε_{0} = k ε_{0}$ , $F/m$ mein measure ki gayi.

Ek subscript material ka naam deta hai: $ε_{s i} = k_{s i} ε_{0}$ = silicon, $ε_{o x} = k_{o x} ε_{0}$ = gate oxide.

Picture: $ε$ (equivalently $k$ ) ko socho ki material field lines ke liye kitni "soft" hai — high- $k$ material field lines ko aasaani se pass hone deta hai.
Topic ko iska zaroorat kyun: ladaai hai "gate field vs drain field." Har side kitna acchi tarah jeette hai woh depend karta hai un layers ki permittivities par jo fields cross karti hain. Isliye $λ$ mein ek ratio $ε_{s i} / ε_{o x} = k_{s i} / k_{o x}$ hota hai — aur kyunki yeh ratio hai, $ε_{0}$ cancel ho jaata hai, sirf pure $k$ ratio bachta hai.

$t_{o x}$ — oxide thickness

5. $λ$ family — har geometry ke liye ek formula

Parent note ek device-specific $λ$ ka promise karta hai. Yahan poora family hai, number-of-gate-sides ke hisaab se ek member, toh koi case guess nahin karna padta. Har ek usi recipe se aata hai (neeche), sirf isme fark hota hai ki kitne sides potential fix karte hain.

Formula Teen screening lengths

Single-gate (planar, 1 side) — thickness $t_{s i}$ ka flat slab: $λ_{s in g l e} = \frac{ε _{s i}}{ε _{o x}} t_{o x} t_{s i}$ Double-gate / tri-gate style (opposite/several faces par gate) — thickness $t_{s i}$ ka slab: $λ_{d o u b l e} = \frac{ε _{s i}}{2 ε _{o x}} t_{o x} t_{s i}$ Gate-all-around (4 sides / surrounding) — diameter $d_{s i}$ ka round wire: $λ_{G AA} = \frac{2 ε _{s i} t _{o x} d _{s i} + ε _{o x} d _{s i}^{2}}{16 ε _{o x}}$ Pattern kaise padhen: har extra gripped side denominator mein ek bada number daalta hai ( $1 \to 2 \to 16$ style factors) → chhota $λ$ → chhota allowed $L_{g}$ . GAA form $d_{s i}$ (round wire) use karta hai, single/double forms $t_{s i}$ (flat slab) use karte hain — exactly §1 ki shapes se match karta hai. Dhyan do har version permittivities ka ratio times lengths, sab square root ke neeche hai, toh har ek nm mein nikalta hai.

Recall Square root aur parabolic-potential recipe kahan se aati hai?

Teeno formulas usi tarike se nikale jaate hain. Steps, zero se:

Silicon ke andar field law likho. 2-D Poisson equation kehta hai ki potential $ϕ (x, y)$ charge ke proportion mein curve hota hai; lightly-doped channel mein hum leading approximation ke roop mein iske charge-free cousin (Laplace's equation) use kar sakte hain. Simple words mein: "potential left-to-right kaise bend karta hai plus top-to-bottom kaise bend karta hai — dono balance hone chahiye."
Body ke across shape guess karo (the "ansatz"). Patli body direction ke across hum maante hain ki $ϕ$ ek parabola hai — jahan gate pakadta hai wahan flat, beech mein dip. Kyun parabola: yeh sabse simple curve hai jo symmetric hai aur gripped surface(s) par ek fixed value match kar sakti hai; gate do (ya all-around) edges pin karta hai, aur do pinned edges ke beech parabola hi milta hai.
Boundary condition apply karo — yahan "kitne sides" enter karta hai. Gate potential ko har surface par fix karta hai jo woh touch karta hai. Ek touched face (single-gate) vs opposite faces (double) vs poora perimeter (GAA) change karta hai ki parabola ko kitna curvature supply karna hai — aur yahi exactly denominators mein $1$ vs $2$ vs $16$ factor hai.
Along-channel potential ke liye ek equation pe collapse karo. Parabola ko average karne se 2-D problem ek 1-D equation ban jaati hai $\frac{d ^{2} ψ}{d x ^{2}} = \frac{ψ}{λ ^{2}}$ ke form mein. Constant $λ^{2}$ jo nikalta hai woh do lengths ka product hai (oxide ke across $t_{o x}$ aur body ke across $t_{s i}$ ya $d_{s i}$ ) permittivity ratio se weighted.
Root lo. Kyunki $λ^{2}$ (length $\times$ length) ke roop mein aaya, distance $λ$ iska square root hai — jaise square ki side uske area ka root hoti hai. Yahi ki poori origin hai.

Double-gate ko single-gate ki comparison mein factor 2 kyun milta hai? ::: Gate do opposite faces pakadta hai sirf ek ki jagah, toh parabola dono ends par pinned hai aur aadha penetration chahiye — extra pinned face $λ^{2}$ ko 2 se divide kar deta hai. GAA (round-wire) formula alag kyun dikhta hai, $d_{s i}^{2}$ ke saath? ::: Yeh cylindrical coordinates mein derive kiya gaya hai (diameter $d_{s i}$ ka round wire), flat slab mein nahin, toh geometry ek $d_{s i}$ aur ek $d_{s i}^{2}$ term aur surrounding-gate factor 16 denominator mein produce karti hai.

Gate-All-Around — gate conductor channel ko har side se wrap karta hai.

L_{g}

W_{n s}

T_{n s}

t_{o x}

λ

ki units

Nanometres (nm), kyunki

1 nm = 1 0^{- 9} m

L_{g}

ek sentence mein

Gate ke neeche channel length, source-to-drain measure ki gayi; chhota

L_{g}

dense hai lekin leaky.

W_{n s}

T_{n s}

Sheet ke cross-section rectangle ki width aur thickness — wide dimension vs thin dimension.

Planar / tri-gate / GAA (1 sheet) ke liye

W_{e f f}

W_{n s}

W_{n s} + 2 T_{n s}

2 (W_{n s} + T_{n s})

— sirf woh edges add karo jinhein gate actually touch karta hai.

N

GAA sheets stack karne ka

W_{e f f}

par effect

Multiply karta hai:

W_{e f f, t o t a l} = N \cdot 2 (W_{n s} + T_{n s})

same footprint mein.

λ

kya measure karta hai aur chhota accha hai ya nahin

Drain field channel mein kitni door leak hoti hai; chhota

λ

accha hai; yeh device-specific hai (

λ_{s in g l e}

λ_{d o u b l e}

λ_{G AA}

λ_{G AA}

kaunsa body dimension use karta hai, aur

λ_{s in g l e}

kaunsa?

λ_{G AA}

d_{s i}

(round wire) use karta hai;

λ_{s in g l e}

t_{s i}

(flat slab) use karta hai.

L_{g}

aur

λ

ko jodne wala rule

L_{g} ≳ 5 λ

acche short-channel control ke liye.

k

aur

ε_{r}

— inका kya rishta hai?

Yeh ek hi quantity hain;

k \equiv ε_{r}

, relative permittivity (dielectric constant), aur

ε = k ε_{0}

Absolute vs vacuum permittivity

ε = k ε_{0}

;

ε_{0} \approx 8.85 \times 1 0^{- 12}

F/m vacuum permittivity hai.

Patla

t_{o x}

kyun help karta hai

Gate channel ke paas baithta hai, tighter grip, chhota

λ

Superlattice mein kaunsa material sacrificial hai

SiGe etch hota hai; Si sheets rakhi jaati hain.

Kyun ALD (koi bhi deposition nahin) gate fill karta hai

Yeh ek atomic layer at a time coat karta hai, conformally ek released sheet ke hidden top/bottom/sides tak pahunchta hai.

Gate sides ki sankhya: planar / FinFET / GAA

1 / 3 / 4.

Foundations — Gate-all-around (GAA) nanosheet transistors