Gate-all-around (GAA) nanosheet transistors: Exercises

Before the ladder, let us make the two geometric pictures the whole page rests on explicit.

Figure 1 shows this from above and from the side: the top-down box is the footprint; stacking sheets piles channels into the page's depth, not across the floor.

Figure — Gate-all-around (GAA) nanosheet transistors

Look at the left panel: three sheets sit on the same floor rectangle (dotted) — the footprint is unchanged. The right panel shows one sheet's cross-section, and why the gate-controlled perimeter is $2 (W_{n s} + T_{n s})$ : trace the teal gate around the orange sheet and you cross two long faces ( $W_{n s}$ each) plus two thin edges ( $T_{n s}$ each).

The three tools we lean on the whole way down:

Here $W_{n s}$ is the sheet width (the long horizontal dimension), $T_{n s}$ is the sheet thickness (the short vertical dimension), $L_{g}$ is the gate length (how long the gate is along the current's travel direction), and $N$ is the number of stacked sheets.

Where does the $λ$ formula come from? (an on-page picture, not a black box)

Formula Sketch of the origin (why each term sits where it does)

Inside the channel the potential $ϕ$ obeys the 2-D Poisson/Laplace equation. Scaling theory makes one clean assumption: the potential varies parabolically across the thin channel body (thickness/diameter $d_{s i}$ ). Substituting a parabola into Poisson and applying the boundary condition that the gate fixes the potential on the wrapped surface collapses the 2-D problem into a 1-D equation of the form $\frac{d ^{2} ϕ _{c}}{d x ^{2}} = \frac{ϕ _{c} - ϕ _{g a t e}}{λ ^{2}},$ where $x$ runs source→drain and $ϕ_{c}$ is the channel-centre potential. The constant $λ$ that falls out is exactly the surrounding-gate result quoted in the parent note: $λ_{G AA} = \frac{2 ε _{s i} t _{o x} d _{s i} + ε _{o x} d _{s i}^{2}}{16 ε _{o x}} .$ Reading the terms (each earns its place):

$d_{s i}$ = channel thickness/diameter → a fatter body stores more field, so $λ$ grows with $d_{s i}$ .
$t_{o x}$ = gate-oxide thickness → a thicker oxide weakens the gate's grip, so $λ$ grows with $t_{o x}$ .
the 16 in the denominator is the "all-around" bonus: wrapping every side multiplies the gate's screening, shrinking $λ$ . Fewer gated sides → smaller denominator → larger $λ$ .

Level 1 — Recognition

Recall Solution

GAA nanosheet gate = all 4 sides (it fully surrounds the released sheet).
FinFET (tri-gate) gate = 3 sides (top + two walls; the fin bottom is anchored to the substrate). Compare with FinFET (tri-gate) transistors — the missing 4th side is exactly why a little current still leaks under a fin.

Recall Solution

The SiGe is sacrificial and is etched away; the Si sheets are kept and become the channels. See Epitaxy and SiGe superlattices. The whole trick is an etch chemistry that removes SiGe ~100× faster than Si.

Recall Solution

$W_{e f f, 1} = 2 (W_{n s} + T_{n s}) = 2 (40 + 5)$

$2 W_{n s} = 80$ nm accounts for the two wide faces (top and bottom of the sheet).
$2 T_{n s} = 10$ nm accounts for the two thin edges (left and right). Total $= 90$ nm. (Trace it on Figure 1's right panel.)

Level 2 — Application

Recall Solution

$W_{e f f, 1} = 2 (30 + 6) = 2 (36) = 72 nm$

Recall Solution

One sheet: $2 (25 + 5) = 60$ nm. Four sheets: $W_{e f f, t o t a l} = 4 \times 60 = 240 nm$ Same footprint, 4× the perimeter — that is the "current per unit area" win.

Recall Solution

$L_{g} \geq 5 (3.2) = 16 nm$ So $L_{g} = 16$ nm is the floor. Anything shorter and the drain field reaches across → short-channel leakage (see Short-channel effects and DIBL).

Recall Solution

GAA: $3 \times 2 (30 + 6) = 3 \times 72 = 216 nm$ .
FinFET: $2 (50) + 6 = 106 nm$ .
Ratio: $216/106 \approx 2.04$ → GAA delivers about 2× the effective width in the same footprint. Figure 2 plots this bar comparison.

Level 3 — Analysis

Recall Solution

One sheet: $2 (28 + 6) = 68$ nm. Require $68 N \geq 300 \Rightarrow N \geq 4.41$ . Since $N$ must be a whole number of sheets, $N = 5$ . $W_{e f f, t o t a l} = 5 \times 68 = 340 nm (\geq 300 ✓)$ Why round up, not down: $N = 4$ gives only $272$ nm $< 300$ , so it fails the target.

Recall Solution

Both satisfy $2 (W_{n s} + T_{n s}) = 72$ . But Design B is wider and thinner ( $W_{n s} = 34$ ). A wider sheet means the middle of the sheet is farther from any sidewall, so the gate's grip on the sheet centre is weaker — it drifts toward planar-like behaviour with worse short-channel control (see Subthreshold slope and gate electrostatics). Design A (narrower, thicker) keeps every point of the channel closer to a wrapping gate face. Take-away: equal $W_{e f f}$ does not mean equal electrostatics — geometry (aspect ratio) matters.

Recall Solution

Numerator: $2 (11.7) (1) (5) + 3.9 (5)^{2} = 117 + 97.5 = 214.5$ . Denominator: $16 (3.9) = 62.4$ . $λ_{G AA} = 214.5/62.4 = 3.4375 \approx 1.854 nm$ Floor: $L_{g} \geq 5 (1.854) \approx 9.27 nm$ . Units check: the $ε$ 's cancel (unitless), leaving nm² under the root → $λ$ in nm. ✓ Why $λ$ is this small: wrapping the gate all-around puts a large $ε_{o x}$ -weighted term ( $16 ε_{o x}$ ) in the denominator, shrinking the penetration depth — the drain field simply cannot punch through (see Figure 3).

Level 4 — Synthesis

Recall Solution

(a) GAA: $3 \times 2 (32 + 6) = 3 \times 76 = 228 nm$ . FinFET: $2 (52) + 7 = 111 nm$ . (b) Ratio $= 228/111 \approx 2.05$ → about 2.05× the on-current. (c) The channel release: selectively etching the sacrificial SiGe to leave suspended Si sheets, then conformally filling the gate stack with ALD around every freed surface. Without release, you cannot wrap the 4th side.

Recall Solution

Constraint: $N \cdot 2 (W_{n s} + 5) = 210 \Rightarrow W_{n s} = \frac{210}{2 N} - 5$ .

(i) $N = 3$ : $W_{n s} = \frac{210}{6} - 5 = 35 - 5 = 30 nm$ → wide sheets, few of them (higher drive per sheet, weaker per-sheet control).
(ii) $N = 5$ : $W_{n s} = \frac{210}{10} - 5 = 21 - 5 = 16 nm$ → narrow sheets, more of them (tighter electrostatics, lower power). Why both are valid: same total $W_{e f f} = 210$ nm, but different geometry gives the designer the drive-vs-control dial that a fixed-height FinFET could not offer.

Recall Solution

FinFET floor: $5 \times 5 = 25$ nm. GAA floor: $5 \times 3.5 = 17.5$ nm. Headroom $= 25 - 17.5 = 7.5 nm$ shorter. Percentage reduction $= \frac{7.5}{25} \times 100 = 30%$ . Why it matters: a 30% shorter allowed gate means denser, faster logic without losing switching (lower DIBL, steeper subthreshold slope).

Level 5 — Mastery

Recall Solution

Per-sheet width to exactly hit 250: $W_{n s} = \frac{250}{2 N} - 6$ ; using more sheets lets $W_{n s}$ shrink (better control).

$N = 5$ : $W_{n s} = \frac{250}{10} - 6 = 25 - 6 = 19 nm$ → meets $\geq 15$ rule ✓, and gives the narrowest sheets → tightest electrostatics.
Check it clears the target: $5 \times 2 (19 + 6) = 5 \times 50 = 250 nm (\geq 250 ✓)$ .
Why not $N = 4$ ? Then $W_{n s} = \frac{250}{8} - 6 = 31.25 - 6 = 25.25$ nm — wider sheets, weaker control. Larger $N$ is preferred here. Chosen design: $N = 5$ , $W_{n s} = 19 nm$ , $T_{n s} = 6 nm$ , $W_{e f f, t o t a l} = 250 nm$ . Defence: meets width target exactly, uses the maximum available sheet count so each sheet is as narrow as the patterning limit allows (best gate grip), and $19 nm \geq 15 nm$ so it is manufacturable.

Recall Solution

Chain: more gate coverage (4 sides vs 3) → the drain field is screened on every face → smaller screening length $λ$ → smaller minimum $L_{g}$ ( $L_{g} \geq 5 λ$ ) → shorter, denser transistors with less DIBL and leakage and a steeper subthreshold slope. Enabling step: the SiGe channel release (selective etch of the sacrificial SiGe grown by Epitaxy and SiGe superlattices), which frees the Si sheets so the gate can wrap the 4th side. Deposition it depends on: Atomic Layer Deposition (ALD) — self-limiting and conformal — to line the High-k metal gate stack into the narrow suspended gaps top, bottom and sides. This same stacking-and-wrapping logic scales onward to CFET (complementary FET).

Flashcards

Single-sheet effective width for

W_{n s} = 30, T_{n s} = 6

2 (30 + 6) = 72

nm.

Minimum

L_{g}

when

λ = 3.2

nm and

L_{g} \geq 5 λ

16

nm.

Minimum integer sheets

N

for

W_{e f f} \geq 300

with per-sheet 68 nm?

N = 5

(since

68 \times 4 = 272 < 300

Percentage

L_{g}

-floor reduction from

λ = 5

λ = 3.5

30%

(25 nm → 17.5 nm).

What does the stacking formula give at

N = 1

Exactly

W_{e f f, 1} = 2 (W_{n s} + T_{n s})

— it collapses to a single sheet.

Are

ε_{s i}

and

ε_{o x}

unit-bearing?

No — they are relative permittivities, unitless ratios (

11.7

and

3.9

Why does equal

W_{e f f}

not mean equal electrostatics?

A wider, thinner sheet puts its centre farther from any gate face, weakening short-channel control.

Where does the λ formula come from? (an on-page picture, not a black box)

Level 1 — Recognition

Level 2 — Application

Level 3 — Analysis

Level 4 — Synthesis

Level 5 — Mastery

Flashcards

Where does the $λ$ formula come from? (an on-page picture, not a black box)