Gate-all-around (GAA) nanosheet transistors: Exercises

4.3.20 · D4 · Hardware › Semiconductor Fabrication › Gate-all-around (GAA) nanosheet transistors

Ladder shuru karne se pehle, do geometric pictures ko explicitly samajh lete hain jinpe poora page tika hai.

Figure 1 yeh upar se aur side se dikhata hai: top-down box footprint hai; sheets ko stack karna channels ko page ki depth mein pile karta hai, floor ke across nahi.

Figure — Gate-all-around (GAA) nanosheet transistors

Left panel dekho: teen sheets same floor rectangle (dotted) pe baithi hain — footprint unchanged hai. Right panel ek sheet ka cross-section dikhata hai, aur kyun gate-controlled perimeter $2 (W_{n s} + T_{n s})$ hai: teal gate ko orange sheet ke around trace karo aur aap do long faces ( $W_{n s}$ each) plus do thin edges ( $T_{n s}$ each) cross karte ho.

Teen tools jinhe hum poore time use karte hain:

Yahan $W_{n s}$ sheet ki width hai (lamba horizontal dimension), $T_{n s}$ sheet ki thickness hai (chhota vertical dimension), $L_{g}$ gate length hai (current ke travel direction ke along gate kitna lamba hai), aur $N$ stacked sheets ki number hai.

$λ$ formula kahan se aata hai? (page pe ek picture, black box nahi)

Formula Origin ki sketch (kyun har term wahan hai jahan hai)

Channel ke andar potential $ϕ$ 2-D Poisson/Laplace equation follow karta hai. Scaling theory ek clean assumption banati hai: potential thin channel body (thickness/diameter $d_{s i}$ ) across parabolically vary karta hai. Poisson mein ek parabola substitute karke aur boundary condition apply karke ki gate wrapped surface pe potential fix karta hai, 2-D problem ek 1-D equation mein collapse ho jaati hai: $\frac{d ^{2} ϕ _{c}}{d x ^{2}} = \frac{ϕ _{c} - ϕ _{g a t e}}{λ ^{2}},$ jahan $x$ source→drain run karta hai aur $ϕ_{c}$ channel-centre potential hai. Jo constant $λ$ nikalta hai woh exactly surrounding-gate result hai jo parent note mein quoted hai: $λ_{G AA} = \frac{2 ε _{s i} t _{o x} d _{s i} + ε _{o x} d _{s i}^{2}}{16 ε _{o x}} .$ Terms padhna (har ek apni jagah earn karta hai):

$d_{s i}$ = channel thickness/diameter → mota body zyada field store karta hai, isliye $λ$ $d_{s i}$ ke saath barhta hai.
$t_{o x}$ = gate-oxide thickness → mota oxide gate ki grip kamzor karta hai, isliye $λ$ $t_{o x}$ ke saath barhta hai.
denominator mein 16 "all-around" bonus hai: har side ko wrap karna gate ki screening ko multiply karta hai, $λ$ ko shrink karta hai. Kam gated sides → chhota denominator → bada $λ$ .

Level 1 — Recognition

Recall Solution

GAA nanosheet gate = all 4 sides (yeh released sheet ko fully surround karta hai).
FinFET (tri-gate) gate = 3 sides (top + do walls; fin bottom substrate se anchored hai). FinFET (tri-gate) transistors se compare karo — missing 4th side exactly wahi wajah hai ki fin ke neeche thoda current abhi bhi leak karta hai.

Recall Solution

SiGe sacrificial hai aur etch away kiya jaata hai; Si sheets rakhi jaati hain aur channels ban jaati hain. Dekho Epitaxy and SiGe superlattices. Poora trick ek etch chemistry hai jo SiGe ko Si se ~100× zyada fast remove karti hai.

Recall Solution

$W_{e f f, 1} = 2 (W_{n s} + T_{n s}) = 2 (40 + 5)$

$2 W_{n s} = 80$ nm do wide faces (sheet ka top aur bottom) ke liye account karta hai.
$2 T_{n s} = 10$ nm do thin edges (left aur right) ke liye account karta hai. Total $= 90$ nm. (Figure 1 ke right panel pe trace karo.)

Level 2 — Application

Recall Solution

$W_{e f f, 1} = 2 (30 + 6) = 2 (36) = 72 nm$

Recall Solution

Ek sheet: $2 (25 + 5) = 60$ nm. Char sheets: $W_{e f f, t o t a l} = 4 \times 60 = 240 nm$ Same footprint, 4× perimeter — yahi "current per unit area" ki jeet hai.

Recall Solution

$L_{g} \geq 5 (3.2) = 16 nm$ Toh $L_{g} = 16$ nm floor hai. Isse chhota kuch bhi aur drain field across pohonchega → short-channel leakage (dekho Short-channel effects and DIBL).

Recall Solution

GAA: $3 \times 2 (30 + 6) = 3 \times 72 = 216 nm$ .
FinFET: $2 (50) + 6 = 106 nm$ .
Ratio: $216/106 \approx 2.04$ → GAA same footprint mein lagbhag 2× effective width deliver karta hai. Figure 2 yeh bar comparison plot karta hai.

Level 3 — Analysis

Recall Solution

Ek sheet: $2 (28 + 6) = 68$ nm. Require $68 N \geq 300 \Rightarrow N \geq 4.41$ . Kyunki $N$ poora number of sheets hona chahiye, $N = 5$ . $W_{e f f, t o t a l} = 5 \times 68 = 340 nm (\geq 300 ✓)$ Neeche kyun nahi round karte: $N = 4$ sirf $272$ nm $< 300$ deta hai, isliye yeh target fail karta hai.

Recall Solution

Dono $2 (W_{n s} + T_{n s}) = 72$ satisfy karte hain. Lekin Design B wider aur thinner hai ( $W_{n s} = 34$ ). Ek wider sheet matlab sheet ka middle kisi bhi sidewall se zyada door hai, isliye gate ki sheet centre pe grip kamzor hai — yeh worse short-channel control ke saath planar-like behaviour ki taraf drift karta hai (dekho Subthreshold slope and gate electrostatics). Design A (narrower, thicker) channel ke har point ko wrapping gate face ke kareeb rakhta hai. Take-away: equal $W_{e f f}$ ka matlab equal electrostatics nahi — geometry (aspect ratio) matter karta hai.

Recall Solution

Numerator: $2 (11.7) (1) (5) + 3.9 (5)^{2} = 117 + 97.5 = 214.5$ . Denominator: $16 (3.9) = 62.4$ . $λ_{G AA} = 214.5/62.4 = 3.4375 \approx 1.854 nm$ Floor: $L_{g} \geq 5 (1.854) \approx 9.27 nm$ . Units check: $ε$ 's cancel ho jaate hain (unitless), root ke andar nm² bachta hai → $λ$ nm mein. ✓ $λ$ itna chhota kyun hai: gate ko all-around wrap karna denominator mein ek bada $ε_{o x}$ -weighted term ( $16 ε_{o x}$ ) rakhta hai, penetration depth ko shrink karta hai — drain field simply punch through nahi kar sakta (dekho Figure 3).

Level 4 — Synthesis

Recall Solution

(a) GAA: $3 \times 2 (32 + 6) = 3 \times 76 = 228 nm$ . FinFET: $2 (52) + 7 = 111 nm$ . (b) Ratio $= 228/111 \approx 2.05$ → lagbhag 2.05× on-current. (c) Channel release: sacrificial SiGe ko selectively etch karna taaki suspended Si sheets bach jaayein, phir ALD ke saath har freed surface ke around conformally gate stack fill karna. Release ke bina, aap 4th side wrap nahi kar sakte.

Recall Solution

Constraint: $N \cdot 2 (W_{n s} + 5) = 210 \Rightarrow W_{n s} = \frac{210}{2 N} - 5$ .

(i) $N = 3$ : $W_{n s} = \frac{210}{6} - 5 = 35 - 5 = 30 nm$ → wide sheets, kam unki number (per sheet zyada drive, per-sheet control kamzor).
(ii) $N = 5$ : $W_{n s} = \frac{210}{10} - 5 = 21 - 5 = 16 nm$ → narrow sheets, unki zyada number (tighter electrostatics, lower power). Kyun dono valid hain: same total $W_{e f f} = 210$ nm, lekin different geometry designer ko woh drive-vs-control dial deti hai jo ek fixed-height FinFET offer nahi kar sakta.

Recall Solution

FinFET floor: $5 \times 5 = 25$ nm. GAA floor: $5 \times 3.5 = 17.5$ nm. Headroom $= 25 - 17.5 = 7.5 nm$ chhota. Percentage reduction $= \frac{7.5}{25} \times 100 = 30%$ . Kyun matter karta hai: 30% chhota allowed gate matlab denser, faster logic switching khoye bina (lower DIBL, steeper subthreshold slope).

Level 5 — Mastery

Recall Solution

250 exactly hit karne ke liye per-sheet width: $W_{n s} = \frac{250}{2 N} - 6$ ; zyada sheets use karne se $W_{n s}$ shrink ho sakti hai (better control).

$N = 5$ : $W_{n s} = \frac{250}{10} - 6 = 25 - 6 = 19 nm$ → $\geq 15$ rule meet karta hai ✓, aur narrowest sheets deta hai → tightest electrostatics.
Check karo ki target clear karta hai: $5 \times 2 (19 + 6) = 5 \times 50 = 250 nm (\geq 250 ✓)$ .
$N = 4$ kyun nahi? Tab $W_{n s} = \frac{250}{8} - 6 = 31.25 - 6 = 25.25$ nm — wider sheets, kamzor control. Yahan bada $N$ prefer kiya jaata hai. Chosen design: $N = 5$ , $W_{n s} = 19 nm$ , $T_{n s} = 6 nm$ , $W_{e f f, t o t a l} = 250 nm$ . Defence: width target exactly meet karta hai, maximum available sheet count use karta hai taaki har sheet utni narrow ho jitni patterning limit allow kare (best gate grip), aur $19 nm \geq 15 nm$ hai isliye manufacturable hai.

Recall Solution

Chain: zyada gate coverage (4 sides vs 3) → drain field har face pe screen hota hai → chhota screening length $λ$ → chhota minimum $L_{g}$ ( $L_{g} \geq 5 λ$ ) → chhote, denser transistors kam DIBL aur leakage ke saath aur ek steeper subthreshold slope ke saath. Enabling step: SiGe channel release (Epitaxy and SiGe superlattices se grown sacrificial SiGe ka selective etch), jo Si sheets ko free karta hai taaki gate 4th side wrap kar sake. Deposition jis par depend karta hai: Atomic Layer Deposition (ALD) — self-limiting aur conformal — High-k metal gate stack ko narrow suspended gaps mein top, bottom aur sides conform karne ke liye. Yahi stacking-and-wrapping logic aage CFET (complementary FET) tak scale hoti hai.

Flashcards

W_{n s} = 30, T_{n s} = 6

ke liye single-sheet effective width kya hai?

2 (30 + 6) = 72

nm.

λ = 3.2

nm aur

L_{g} \geq 5 λ

hone par minimum

L_{g}

kya hai?

16

nm.

Per-sheet 68 nm ke saath

W_{e f f} \geq 300

ke liye minimum integer sheets

N

kitne?

N = 5

(kyunki

68 \times 4 = 272 < 300

λ = 5

λ = 3.5

tak percentage

L_{g}

-floor reduction kitni hai?

30%

(25 nm → 17.5 nm).

Stacking formula

N = 1

pe kya deta hai?

Exactly

W_{e f f, 1} = 2 (W_{n s} + T_{n s})

— single sheet pe collapse ho jaata hai.

Kya

ε_{s i}

aur

ε_{o x}

unit-bearing hain?

Nahi — yeh relative permittivities hain, unitless ratios (

11.7

aur

3.9

Equal

W_{e f f}

ka matlab equal electrostatics kyun nahi?

Ek wider, thinner sheet ka centre kisi bhi gate face se zyada door hota hai, short-channel control kamzor hota hai.

λ formula kahan se aata hai? (page pe ek picture, black box nahi)

Level 1 — Recognition

Level 2 — Application

Level 3 — Analysis

Level 4 — Synthesis

Level 5 — Mastery

Flashcards

$λ$ formula kahan se aata hai? (page pe ek picture, black box nahi)