Question bank — Gate-all-around (GAA) nanosheet transistors

TRUE — sheet release (suspend) hoti hai, isliye gate metal top, bottom, aur dono edges ko wrap karta hai; woh poora wrap hi "gate-all-around" ka poora point hai.

FALSE — ek FinFET sirf 3 taraf se pakad ta hai (top aur do walls); fin ka bottom substrate se anchored rehta hai, isliye drain abhi bhi us unguarded face ke through pahunch sakta hai. Dekho FinFET (tri-gate) transistors.

FALSE — SiGe sacrificial hai aur etch out hota hai; Si sheets channel ke roop mein rakhti hain. Ise ulta samajhna classic exam trap hai.

TRUE — chhota $\lambda$ matlab drain field kam ghuspta hai, isliye gate tug-of-war jeetta hai; isliye rule $L_g\gtrsim 5\lambda$ ek chhothe $\lambda$ ko chhotha gate allow karta hai.

FALSE — sheets usi floor area mein vertically stack hoti hain, isliye current badhta hai jabki footprint fixed rehta hai; woh "zyada current per unit area" GAA ki headline win hai.

FALSE — wide sheets drive current badhati hain lekin sheet ke middle (edges se door) mein electrostatic grip kamzor ho jaati hai, short-channel control kharaab hoti hai; yeh trade-off hai, free win nahi.

FALSE — ek narrow gap mein suspended sheet ke neeche coat karna padta hai; sirf self-limiting, conformal Atomic Layer Deposition (ALD) hi har surface tak uniformly pahunchti hai.

TRUE — same all-around gate idea; ek nanosheet ek wide thin slab hai, ek nanowire ek narrow thin wire hai, aur dono GAA channels hain.

Galat part "identical" hai — FinFET ka channel apne base pe attached hai (3-side control), jabki GAA channel released/suspended hai isliye gate 4th side close karta hai; woh extra surface genuinely alag electrostatic situation hai, koi rotation nahi.

Ulta hai — SiGe remove hota hai (woh sahi chemistry mein ~100× faster etch hota hai) aur Si surviving channel hai. Poori mushkil ek aisi etch dhundhne mein hai jo Si ko bachaaye aur SiGe ko kha jaaye.

$\lambda$ drain ki reach measure karta hai, gate ki nahi — bada $\lambda$ matlab drain gehraai mein ghusta hai aur leakage cause karta hai, isliye bada $\lambda$ kharaab hai.

Dummy gate temporary hai — woh processing ke dauran channel region ko hold karta hai aur baad mein remove kiya jaata hai taaki real high-k metal gate ek gate-last flow mein fill ho sake. Dekho High-k metal gate stack.

Factor 2 missing hai — gate full perimeter wrap karta hai, isliye dono long faces aur dono thin edges count hote hain: $W_{eff}=2(W_{ns}+T_{ns})$.

"Perfectly" zyada strong hai — GAA reduces DIBL versus FinFET $\lambda$ shrink karke, lekin drain field sirf screen hota hai, kabhi fully eliminate nahi hota; dekho Short-channel effects and DIBL.

Alternating crystalline stack epitaxy se grow karna padta hai taaki har layer crystal lattice inherit kare; ek random sputtered film woh clean superlattice nahi banata jo chahiye. Dekho Epitaxy and SiGe superlattices.

Zyada gate coverage matlab tighter electrostatic control, isliye gate voltage ka chhota sa change channel ko off se on fast swing karta hai — current ka ek decade ke liye kam volts lagte hain. Dekho Subthreshold slope and gate electrostatics.

Gate ko ek narrow gap ke andar suspended sheet ki underside coat karni padti hai; ALD ek waqt mein ek self-limiting atomic layer banata hai, isliye woh shadowed surfaces tak pahunchta hai jo line-of-sight methods miss kar deti hain.

Tum current set karte ho $W_{ns}$ choose karke (wide = high drive, narrow = low power) design time pe, jabki FinFET ki drive uski fixed fin height se locked hai — tum sirf poore fins add kar sakte the.

Drain field roughly $\lambda$ par decay karta hai, isliye kaafi $\lambda$ lamba gate ensure karta hai ki channel ka middle "gate territory" mein deep ho jahaan drain ka exponentially-faded influence negligible hai.

SiGe ko remove karna exactly woh hai jo silicon sheet ko free karta hai taaki gate 4th (bottom) side wrap kar sake — uske bina tum sirf kabhi FinFET-style 3-side control hi paate.

Ek high-k layer gate ko physically thicker film ke saath channel se strongly couple karne deta hai, leakage cut karta hai aur tight control rakhta hai — conformal ALD fill ke saath naturally pair karta hai. Dekho High-k metal gate stack.

Woh planar behaviour ki taraf degrade ho jaata hai — bahut wide sheet ka middle kisi bhi edge-gate influence se door hota hai, isliye sirf top/bottom faces hi control rakh sakti hain, aur DIBL wapas aa jaata hai.

Tum abhi bhi full all-around control aur clean switching paate ho, lekin tum current-per-area advantage sacrifice karte ho — tum same footprint use kar rahe ho sirf ek sheet ke $W_{eff}$ ke liye.

Si sheets thin, roughen, ya break ho jaati hain, $T_{ns}$ aur $W_{eff}$ change ho jaata hai aur yield hurt hoti hai — isliye etch-chemistry selectivity make-or-break step hai.

$\lambda$ bhi shrink hota hai — ek thinner body drain field ko sneakily ghusne ke liye kahin nahi chodti, jo best short-channel immunity deta hai (harder fabrication aur higher resistance ki cost pe).

Nahi — tall stacks SiGe/Si epitaxy ko strain karte hain, release etch aur gate fill ko innermost gaps tak pahunchna mushkil banate hain, aur eventually parasitics aur defects useful stack height cap kar dete hain.

Woh natural agla step hai, CFET, jo complementary transistors ko vertically stack karta hai aur bhi zyada density ke liye; all-around release/fill toolkit seedha carry over hoti hai. Dekho CFET (complementary FET).