Gate-all-around (GAA) nanosheet transistors: Worked examples

4.3.20 · D3 · Hardware › Semiconductor Fabrication › Gate-all-around (GAA) nanosheet transistors

Parent dekho: Gate-all-around (GAA) nanosheet transistors.

Scenario matrix

Neeche har worked example us table ki cell ke saath tagged hai jise woh cover karta hai. Milkar yeh har cell fill karte hain.

Cell	Case class	Kya special hai	Example
A	Ordinary width	plain numbers, ek sheet	Ex 1
B	Stacking ( $N$ sheets)	$N$ se multiply karo, same footprint	Ex 2
C	Degenerate: square ( $W_{n s} = T_{n s}$ )	sheet → nanowire limit	Ex 3
D	Zero / limiting ( $T_{n s} \to 0$ )	thinnest possible sheet	Ex 4
E	Cross-over / tie	GAA $W_{e f f}$ = FinFET $W_{e f f}$	Ex 5
F	Screening length $λ$	$λ$ formula mein plug karo, sab signs positive	Ex 6
G	Word problem (design target)	"current spec ke liye kitni sheets chahiye?"	Ex 7
H	Exam twist / trap	wide-sheet trade-off, "zyada matlab worse"	Ex 8

Worked examples

Worked example Example 1 — Ordinary single sheet

(Cell A) Ek nanosheet ki width $W_{n s} = 40 nm$ aur thickness $T_{n s} = 5 nm$ hai. Ek sheet ke liye $W_{e f f}$ nikalo.

Forecast: guess karo — kya yeh 40 ke paas hoga, 80 ke paas, ya 90 nm ke paas?

Gate jo perimeter wrap karta hai usse identify karo. Yeh step kyun? GAA control all-around hai, isliye gate rectangle ke charon edges ko touch karta hai — transistor jo width "feel" karta hai woh poora perimeter hai, sirf top nahi.
Do lambe sides: $2 W_{n s} = 2 \times 40 = 80 nm$ . Yeh step kyun? Yeh wide top aur bottom faces hain.
Do patli edges: $2 T_{n s} = 2 \times 5 = 10 nm$ . Yeh step kyun? Yeh do narrow vertical sidewalls hain.
Add karo: $W_{e f f} = 80 + 10 = 90 nm$ . Yeh step kyun? Perimeter $= 2 (W_{n s} + T_{n s})$ .

Verify: $2 (40 + 5) = 2 (45) = 90 nm$ . Units: andar nm + nm, ×2 → nm. ✅ 40 se bada hai (humne edges add kiye), $4 \times 40$ se chhota — sane hai.

Figure — Gate-all-around (GAA) nanosheet transistors

Worked example Example 3 — Degenerate: square cross-section (nanowire limit)

(Cell C) Sheet ko tab tak shrink karo jab tak width thickness ke barabar ho jaaye: $W_{n s} = T_{n s} = 8 nm$ . $W_{e f f}$ nikalo aur batao yeh device kya ban gaya hai.

Forecast: ek "wide slab" formula ko square feed kiya — kya yeh phir bhi sense karta hai?

Equal values plug karo: $W_{e f f} = 2 (8 + 8) = 32 nm$ . Yeh step kyun? Perimeter formula ko parwah nahi ki shape square hai — yeh bas perimeter hai.
Shape ko pehchano: ek square (nearly circular) cross-section ek nanowire hai, nanosheet nahi. Yeh step kyun? Parent definition kehti hai patli wire = nanowire; formula gracefully usmein degrade ho jaata hai.
Equal area diameter wale circle se cross-check karo: side $8$ wale square ka perimeter $32$ hai; diameter $8$ wale circle ka perimeter $π \cdot 8 \approx 25.1 nm$ hai. Yeh step kyun? Confirm karta hai ki square case sensibly round-wire case ke paas baitha hai.

Verify: $2 (8 + 8) = 32 nm$ . Square perimeter $= 4 \times 8 = 32$ ✅ (match karta hai). Formula sheet→wire boundary par valid rehta hai.

Worked example Example 4 — Zero / limiting: impossibly thin sheet

(Cell D) $W_{n s} = 40 nm$ lo aur $T_{n s} \to 0$ hone do. $W_{e f f}$ kya approach karta hai, aur physically iska kya matlab hai?

Forecast: jab thickness vanish ho, kya width bhi vanish ho jaati hai?

Limit substitute karo: $W_{e f f} = 2 (40 + 0) = 80 nm$ . Yeh step kyun? $T_{n s} = 0$ set karna do edge contributions hata deta hai.
Interpret karo: sirf top + bottom faces bachte hain; gate zero height ki sheet ke around wrap karta hai. Yeh step kyun? $2 T_{n s} \to 0$ matlab vertical sidewalls gayab ho jaate hain — "all-around" collapse hokar "top+bottom" ban jaata hai.
Physical caution: truly zero-thickness sheet conduct karne ke liye koi body nahi hai — yeh ek math limit hai, fabricable device nahi. Yeh step kyun? Case coverage mein flag karna zaroori hai jab number real ho lekin device ho nahi.

Verify: $lim_{T_{n s} \to 0} 2 (40 + T_{n s}) = 80 nm$ . Sanity: patli sheet ⇒ chhota $W_{e f f}$ ( $2 T_{n s}$ remove kiya), monotone aur finite. ✅

Worked example Example 5 — Cross-over / tie: GAA aur FinFET kab equal hote hain?

(Cell E) Ek FinFET ka $W_{e f f}^{F in} = 2 H_{f in} + W_{f in}$ hai jisme $H_{f in} = 50 nm$ , $W_{f in} = 6 nm$ → $W_{e f f}^{F in} = 106 nm$ . GAA ko match karne ke liye kitni stacked sheets ( $W_{n s} = 30$ , $T_{n s} = 6$ ) chahiye?

Forecast: ek sheet? do? teen?

FinFET width: $2 (50) + 6 = 106 nm$ . Yeh step kyun? Tri-gate do 50-nm walls + 6-nm top wrap karta hai.
Ek GAA sheet: $2 (30 + 6) = 72 nm$ . Yeh step kyun? Ek released sheet ka perimeter.
Solve karo $72 N \geq 106 \Rightarrow N \geq 1.47$ . Yeh step kyun? Poori sheets chahiye, isliye round up karo.
Toh $N = 2$ sheets ( $144 nm$ ) pehla count hai jo FinFET ko beat karta hai; $N = 1$ ( $72$ ) haarta hai. Yeh step kyun? Tie 1 aur 2 sheets ke beech mein hai — 1.47 sheets nahi ho sakti.

Verify: $N = 1$ : $72 < 106$ (haarta hai). $N = 2$ : $144 > 106$ (jeetता hai). Cross-over at $N = 106/72 \approx 1.472$ . ✅

Worked example Example 6 — Screening length

$λ$ , sab inputs positive (Cell F) Surrounding-gate wire ke liye use karo $λ_{G AA} = \frac{2 ε _{s i} t _{o x} d _{s i} + ε _{o x} d _{s i}^{2}}{16 ε _{o x}} .$ Lo $ε_{s i} = 11.7$ , $ε_{o x} = 3.9$ , $t_{o x} = 1 nm$ , $d_{s i} = 8 nm$ (sab $ε$ relative hain, isliye unitless; lengths nm mein). $λ_{G AA}$ nikalo.

Forecast: kya $λ$ 3–4 nm ke paas aayega (parent ka "good" range)?

Numerator term 1: $2 ε_{s i} t_{o x} d_{s i} = 2 \times 11.7 \times 1 \times 8 = 187.2$ . Yeh step kyun? Yeh term drain field hai jo body ke upar oxide ke through leak ho rahi hai.
Numerator term 2: $ε_{o x} d_{s i}^{2} = 3.9 \times 64 = 249.6$ . Yeh step kyun? Yeh term silicon body ke andar spread hone wala field hai.
Numerator sum $= 187.2 + 249.6 = 436.8$ ; denominator $= 16 \times 3.9 = 62.4$ . Yeh step kyun? $16$ "all-around" bonus hai — yeh single-gate ke comparison mein $λ$ ko shrink karta hai.
$λ = 436.8/62.4 = 7.0 \approx 2.646 nm$ . Yeh step kyun? Square root lo; units $nm^{2} = nm$ hain.
Rule of thumb: $L_{g} \geq 5 λ \approx 13.2 nm$ . Yeh step kyun? $λ$ ko minimum safe gate length mein convert karta hai.

Verify: $436.8/62.4 = 7.0$ , $7.0 = 2.6458 nm$ , "good" (small) band mein hai. Root ke andar units: (nm·nm inside) / (unitless) → nm² → nm. ✅ Dekho Short-channel effects and DIBL.

Worked example Example 7 — Word problem: current target hit karna

(Cell G) Ek logic cell ko ek on-current chahiye jo total gate width ke saath scale kare. Spec kehta hai $W_{e f f, t o t a l} \geq 200 nm$ . Tumhara process $W_{n s} = 45 nm$ , $T_{n s} = 5 nm$ ki sheets deta hai. Kitni sheets stack karni hogi?

Forecast: do sheets, teen, ya chaar?

Per-sheet width: $2 (45 + 5) = 100 nm$ . Yeh step kyun? Ek sheet ka perimeter — woh width unit jise hum stack karte hain.
Required count: $N \geq 200/100 = 2$ . Yeh step kyun? Total width $N \times 100$ hai; $N$ ke liye solve karo.
Exactly $N = 2$ spec ko $200 nm$ par meet karta hai (koi rounding nahi chahiye). Yeh step kyun? $200$ , $100$ ka exact multiple hai, isliye hum boundary par exactly land karte hain.
Footprint check: stacking vertical hai → floor area unchanged. Yeh step kyun? Confirm karta hai ki humne current spec ko bina area kharcha kiye meet kiya — stack kaise grow hota hai iske liye dekho Epitaxy and SiGe superlattices.

Verify: $2 \times 2 (45 + 5) = 2 \times 100 = 200 nm \geq 200$ . ✅ $N = 1$ sirf $100 < 200$ deta hai (fail), isliye 2 minimal hai.

Worked example Example 8 — Exam twist / trap: kya wider sheet hamesha jeeetta hai?

(Cell H) Design A: ek sheet $W_{n s} = 60$ , $T_{n s} = 6$ . Design B: ek sheet $W_{n s} = 30$ , $T_{n s} = 6$ . Dono ka $W_{e f f}$ compute karo. Trap: kis ka short-channel control better hai, aur kyun bada $W_{e f f}$ automatically "better" nahi hai?

Forecast: wide wale ke paas zyada width hai — kya woh better transistor hai?

Design A: $2 (60 + 6) = 132 nm$ . Yeh step kyun? Wide sheet ka perimeter.
Design B: $2 (30 + 6) = 72 nm$ . Yeh step kyun? Narrow sheet ka perimeter.
Wide sheet A ke paas zyada drive current hai (bada $W_{e f f}$ ). Yeh step kyun? On-current $\propto W_{e f f}$ .
Lekin bahut wide sheet ke middle wala hissa do patli sidewall gates se bahut door hota hai, isliye woh sidewalls use kam control karte hain — electrostatics kamzor ho jaati hai aur yeh planar behaviour ki taraf drift karta hai (worse control). Yeh step kyun? Yahi drive-current-vs-control trade-off hai jo parent ne flag kiya tha; zyada width ≠ strictly better.

Verify: $2 (60 + 6) = 132$ , $2 (30 + 6) = 72$ , aur $132 > 72$ (A wider hai). Trap qualitative hai: bada $W_{e f f}$ lekin per-unit-width control kamzor. Dekho Subthreshold slope and gate electrostatics. ✅

Recall

Recall Har formula ne kaunsi cell stress ki?

Ek sheet ki width kaise milti hai? ::: perimeter $2 (W_{n s} + T_{n s})$ (Cell A). Stack ki width kaise milti hai? ::: $N$ se multiply karo: $N \cdot 2 (W_{n s} + T_{n s})$ (Cell B). Square (wire) cross-section ke liye formula kya hota hai? ::: yeh phir bhi perimeter ke barabar hai, $2 (W + T) = 4 W$ jab $W = T$ (Cell C). Kya bada $W_{e f f}$ hamesha better hai? ::: Nahi — wide sheets short-channel control kho deti hain (Cell H trade-off). Chhota ya bada $λ$ accha hai? ::: Chhota — drain field across nahi pahunch sakta (Cell F).