Gate-all-around (GAA) nanosheet transistors

4.3.20 · Hardware › Semiconductor Fabrication

GAA kyun exist karta hai? (Wo problem jo isse solve hoti hai)

Electrostatic control ladder (kya better hota hai har step mein):

Device	Gate sides	Best control
Planar	1	sabse kharab
FinFET (tri-gate)	3	accha
GAA nanosheet	4 (all-around)	sabse best

Nanosheet kya hota hai? (Definitions)

Ye banta kaise hai? (Key process trick)

Process flow (har step mein kyun):

Epitaxy: alternating Si / SiGe layers grow karo. Kyun: SiGe, Si se ~100× tez etch hota hai sahi chemistry mein → ek built-in "mujhe hatao" marker.
Fin patterning: stack ko narrow fins mein etch karo. Kyun: sheet width $W_{n s}$ define karta hai.
Dummy gate + spacers: ek temporary gate rakho. Kyun: channel region protect karta hai; gate-last flow.
Source/drain recess + epi: doped S/D grow karo. Kyun: carriers ko sabhi sheets mein inject karo.
Channel release: SiGe ko selectively etch karo → floating Si nanosheets. Kyun: yahi ise "all-around" banata hai.
Gate stack fill: high- $k$ dielectric + metal ko ALD (atomic layer deposition) se deposit karo taaki ye conformally har surface coat kare, har sheet ko wrap karte hue. Kyun: ALD atom-thin aur conformal hota hai — narrow gaps mein reach karta hai.

Figure — Gate-all-around (GAA) nanosheet transistors

Physics: GAA control 3-sided se kyun behtar hai

Take-away: Zyada gate coverage → chota $λ$ → drain field screened ho jaata hai → kam DIBL, steeper subthreshold slope, lower leakage.

Common mistakes (Steel-manned)

Flashcards

GAA gate kitni sides control karta hai FinFET gate ke comparison mein?

GAA charon sides control karta hai (surrounding); FinFET 3 sides control karta hai.

Si nanosheets release karne ke liye kaun sa sacrificial material etch kiya jaata hai?

SiGe (selectively etch kiya jaata hai, Si sheets suspended reh jaati hain).

Ek nanosheet jo charon sides se wrap ho uski effective width do.

W_{e f f} = 2 (W_{n s} + T_{n s})

Nanosheets stack karna current kyun badhata hai bina zyada area ke?

Har sheet same footprint mein gate-controlled width ka

\approx 2 (W_{n s} + T_{n s})

add karti hai, toh total

W_{e f f} = N \cdot 2 (W_{n s} + T_{n s})

Kaun sa device parameter drain-field penetration measure karta hai, aur chota accha hai ya bura?

Natural/screening length

λ

; chota

λ

accha hai (drain channel ke across reach nahi kar sakta).

L_{g}

aur

λ

ko link karne wala rule of thumb?

Chahiye

L_{g} ≳ 5 λ

acche short-channel control ke liye.

Kaun sa deposition method suspended sheets ke around gate conformally fill karta hai, aur kyun?

ALD — self-limiting aur conformal, toh ye har released surface coat karta hai.

GAA kaun sa tunable knob deta hai jo FinFET nahi de sakta?

Sheet width

W_{n s}

(continuously drive current vs power/control trade karo), quantized fin height ki jagah.

All-around control ke do short-channel benefits batao.

Lower DIBL aur steeper (nearer-ideal) subthreshold slope ⇒ kam leakage.

Tum SiGe skip karke pure Si sheets float kyun nahi kar sakte?

Fab ke dauran sheets ko kuch hold nahi karega; SiGe ek sacrificial spacer provide karta hai jise baad mein remove karke Si suspend ki jaati hai.

Recall Feynman: 12-saal ke bacche ko explain karo

Ek garden hose (electron path) imagine karo aur tumhara haath usse squeeze karke paani rokta hai. Purane design mein tumhara haath sirf ek side press karta tha aur paani phir bhi leak hota tha. FinFET ne teen sides squeeze kiya. Nayi GAA design mein silicon ki choti flat ribbons hawa mein floating hoti hain, aur "haath" (gate) har ribbon ke poori taraf around wrap hota hai — jaise apni poori mutthi band karna. Best squeeze = kam leak. Aur wo kai ribbons ek doosre ke upar stack karte hain, toh tum same choti jagah mein zyada paani flow lete ho. Clever building trick: wo silicon aur ek helper material (SiGe) stack karte hain, phir sirf helper ko dissolve karte hain toh silicon ribbons free hang karte hain, wrap hone ke liye ready.

Connections

FinFET (tri-gate) transistors — 3-sided control wala predecessor.
Short-channel effects and DIBL — wo problem jo GAA chote $λ$ se fight karta hai.
Atomic Layer Deposition (ALD) — wrap-around gate kaise fill hota hai.
Epitaxy and SiGe superlattices — sheet stack kaise grow hota hai.
High-k metal gate stack — dielectric+metal jo har sheet ko surround karta hai.
Subthreshold slope and gate electrostatics — wo metric jo improve hota hai.
CFET (complementary FET) — agla step: n over p GAA devices stack karna.