4.3.18 · HinglishSemiconductor Fabrication

Process nodes (28nm→7nm→5nm→3nm→2nm)

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4.3.18 · Hardware › Semiconductor Fabrication


Process node KYA hota hai?

Number ka physical meaning KYUN khatam hua:

  • 1970s–2000s mein, "node" ≈ sabse chhoti gate length ≈ half-pitch. Sab kuch saath shrink hota tha (Dennard scaling).
  • 22nm ke aaspaas, flat (planar) transistor ko shrink karna kaam karna band ho gaya — leakage badh gayi. Manufacturers ne sirf shrink karne ki jagah transistor ka shape badla (FinFET, phir GAA). "nm" label marketing continuity ke liye girnaa jaari raha, bhaale gate length ~15–20nm par ruk gayi thi.

Hum shrink kyun karte hain — teen drivers (PPA)

1. Area / density — asli metric

Scratch se derivation: ek logic cell width aur height occupy karta hai, dono roughly pitch se set hote hain. Cell area . Har linear pitch ko se shrink karo: . Fixed die area mein cells ki ginti = (die area)/, toh yeh se multiply ho jata hai. "0.7× linear shrink" per node se density milti hai — yeh wahi classic doubling hai jo Moore's Law ke peeche hai.

2. Power — har switch mein dynamic energy

Derivation: capacitor ko voltage tak charge karne se charge move hota hai aur energy store hoti hai. Usi energy ko discharge mein dissipate kiya jaata hai, isliye ek pura switch cycle dissipate karta hai. Yeh baar per second karo, jab fraction of time node switch kar raha ho, toh milta hai.

KYUN nodes power kam karti hain: chhote transistors → chhota ; naye nodes bhi kam karte hain. Kyunki power par depend karti hai, ko 0.9 V se 0.7 V tak giraane se akela dynamic energy ho jaati hai — 40% saving.

3. Leakage — woh wall jisne planar transistors ko kill kiya


Nodes ke paas transistor ka shape KAISE badla

Figure — Process nodes (28nm→7nm→5nm→3nm→2nm)

KYUN zyada gate coverage help karta hai: gate ka kaam channel ko on/off switch karna hai. Zyada surrounding surface = zyada strong electric field control = transistor bahut chhota hone par bhi poori tarah OFF (low leakage) aur poori tarah ON (high current) hota hai.

Node Year (~) Architecture Notable
28nm 2011 Planar aakhri "long-lived" sasta planar
14/16nm 2014 FinFET pehla FinFET volume
7nm 2018 FinFET pehli EUV use (7nm+/N7)
5nm 2020 FinFET EUV mainstream
3nm 2022–23 FinFET (TSMC N3) / GAA (Samsung) mixed
2nm 2025+ GAA nanosheet + backside power delivery

Worked examples


Common mistakes (steel-manned)


Flashcards

Modern process node name mein "nm" actually kya represent karta hai?
Ek marketing/generation label, kisi single physical transistor dimension se alag (gate length "3nm" par bhi ~15–20nm hai).
Historically kaun si physical quantity node number ke barabar hoti thi?
Half-pitch (repeated metal lines ke beech spacing ka aadha).
Dynamic power formula state karo aur term derive karo.
; ko tak charge karne se store hota hai, discharging mein same dissipate hota hai, isliye ek full cycle dissipate karta hai.
Dennard scaling ~2005 mein kyun break down hui?
Voltage girti nahi reh sakti thi kyunki giraane se subthreshold leakage exponentially badhti hai (), isliye power density badh gayi.
Linear shrink factor ke saath density kaise scale karti hai?
(area 2-D hai), isliye ≈ 2× density.
Node era ke hisaab se transistor architectures order karo.
Planar (≥28nm) → FinFET (22nm–7nm) → GAA/nanosheet (3nm,2nm).
Gate-all-around FinFET se behtar kyun hai?
Gate charon sides se channel wrap karta hai → sabse strong electrostatic control → chhoti lengths par kam leakage.
EUV kya hai aur ~7nm par kyun chahiye thi?
Extreme-UV lithography 13.5nm wavelength par; slow multi-patterning ki jagah single exposure mein fine features print karta hai.
Chhota node necessarily tez clock deta hai?
Nahi — clocks ~3–5GHz par plateau ho gayi; chhote nodes density & efficiency dete hain, na ki bahut zyada .
Companies ke beech nodes compare karne ka sabse accha single metric kaunsa hai?
Transistor density (MTr/mm²), kyunki node names standardized nahi hain.

Recall Feynman: 12-saal ke bacche ko samjhao

Socho ek city bana rahe ho tiny light-switches ki. "28nm" aur "3nm" bas nayi city-building recipes ke naam hain, jaise "2011 recipe" vs "2023 recipe." Nayi recipes aapko usi zameen mein bahut zyada switches pack karne deti hain, aur har switch kam battery use karta hai. Lekin switches itne chhote ho gaye ki ek flat switch "leak" karne laga electricity, bhaale off ho. Toh engineers ne switch ki shape badli, control finger ko poora iske around wrap karke (jaise straw ko ek finger ki jagah poori mutthi se pakadna) taaki woh sahi se band ho. Marketing ke liye naam chhota hota rehta hai, lekin chip par kuch bhi sach mein "3 nanometres" chauda nahi hai.

Connections

Concept Map

originally equalled

everything shrank together

broke planar scaling

implemented as

kept nm label for

now measured by

targets

targets

targets

density scales 1 over k squared

smaller C lower V

V squared term

Process node = marketing name

Half-pitch

Dennard scaling era

Leakage exploded ~22nm

Re-architect transistor shape

FinFET then GAA

PPA drivers

Area / density

Power

Performance

Linear pitch shrink k

Pdyn = alpha C V squared f