Process nodes (28nm→7nm→5nm→3nm→2nm): Question bank

This bank drills the parent topic. For the number-crunching versions of these ideas, that lives in the worked-example decks; here every item is pure concept.

True or false — justify

A "5nm" node means the smallest feature on the chip is 5 nanometres wide.

False. "5nm" is a generation label; the smallest gate at that node is still roughly 16–20 nm. See Moore's Law marketing continuity — the name kept dropping after physical lengths stalled.

The node number historically once did mean a real physical length.

True. In the 1970s–2000s the number tracked the half-pitch (half the spacing between repeated metal lines), which then equalled roughly the gate length while everything shrank together.

A 0.7× linear shrink per generation roughly doubles transistor density.

True. Area is two-dimensional, so density scales as

1/ k^{2}

, and

1/0. 7^{2} \approx 2

— this is the arithmetic behind Moore's Law's "double every ~2 years".

Halving the supply voltage

V

halves the dynamic power.

False. Dynamic power is

P_{dyn} = α C V^{2} f

, which depends on

V^{2}

; halving

V

cuts dynamic power to a quarter (all else equal). This is exactly why voltage reduction is so prized.

Company A's "7nm" and Company B's "7nm" are the same manufacturing capability.

False. Node names are not standardized. Intel's "10nm" density was roughly TSMC's "7nm"; you must compare MTr/mm², not the label.

Moore's Law is a law of physics like

F = ma

False. It's an economic/observational trend (transistors per chip ~2× every ~2 years) sustained by engineering — see Moore's Law. It has no physical force behind it and is now slowing.

Smaller nodes have delivered steadily higher clock frequencies over the last 15 years.

False. Clocks plateaued around 3–5 GHz after ~2005 because

P_{dyn} \propto f

and heat removal is the limit; smaller nodes give more cores and lower power, not much higher

f

Gate-all-around (GAA) wraps the channel more completely than FinFET.

True. See FinFET and GAA transistors: planar touches one face, FinFET wraps three sides, GAA wraps all four — more surrounding surface means stronger electrostatic control.

Dennard scaling failing means we can no longer shrink transistors at all.

False. Shrinking continued; what broke was the constant-power-density promise, because voltage stopped scaling down. We changed transistor shape (FinFET/GAA) to keep going.

EUV lithography was needed because visible-light lasers were too weak.

False. It's about wavelength, not power: resolution scales with

λ

, so EUV Lithography replaced 193 nm deep-UV with 13.5 nm light to print fine features in one shot instead of slow multi-patterning.

Spot the error

"At 3nm, the transistor's gate length is 3nm, which is why leakage is a problem."

The gate length is not 3 nm — it's ~16–20 nm. Leakage is a problem, but the cause is short-channel physics and low

V_{t h}

, not a literal 3 nm gate.

"We can keep lowering supply voltage forever to save power, since

P_{dyn} \propto V^{2}

Ignores Subthreshold leakage. Lowering

V

requires lowering $V_{th}$ to keep speed, and

I_{leak} \propto e^{- q V_{t h} / nk T}

rises exponentially, so static power eventually swamps the dynamic savings.

"Density improvement comes only from making the gate length smaller."

Density is set by the whole 2-D cell (metal pitch, fin/sheet pitch, standard-cell height), not gate length alone. That's why density keeps improving even though gate length stalled around 15–20 nm.

"FinFET was invented mainly to make transistors faster."

Its primary job was electrostatic control to cut leakage at short channels — wrapping the gate around three sides lets the transistor turn fully OFF. Speed/drive benefits are secondary consequences.

"Total chip power is just

α C V^{2} f

That's only the dynamic term. Total is

P = P_{dyn} + V I_{leak}

; the static leakage term is precisely what dominated once voltage scaling stalled.

"Two nodes with the same MTr/mm² must switch at the same speed and power."

Density says nothing directly about speed or leakage. Two nodes can match on density but differ in

V

V_{t h}

, and transistor architecture, giving different power and performance.

Why questions

Why did the "nm" label keep dropping after gate length stopped shrinking?

For marketing continuity — buyers associate a smaller number with a better generation, so makers kept the label falling even though the number no longer maps to any single physical length.

Why does dynamic power depend on

V^{2}

and not just

V

Charging load capacitance

C

to voltage

V

moves charge

Q = C V

and stores energy

\frac{1}{2} C V^{2}

; discharging dissipates the same, so a full switch costs

C V^{2}

— the voltage enters once through charge and once through the potential it's moved across.

Why can't

V_{t h}

(threshold voltage) simply be dropped to allow lower supply voltage?

Because leakage current below threshold grows exponentially,

I_{leak} \propto e^{- q V_{t h} / nk T}

; a small drop in

V_{t h}

causes a large rise in always-on leakage, so static power explodes.

Why did Dennard scaling break down around 2005?

It assumed voltage could shrink with dimensions to keep power density constant. But

V

couldn't fall below ~0.7 V without dropping

V_{t h}

and triggering exponential leakage, so voltage stalled and power density began rising.

Why does wrapping the gate around more sides of the channel reduce leakage?

More surrounding gate surface produces a stronger, more complete electric field over the channel, so the gate can fully deplete/cut off carriers even in a very short channel — the transistor turns properly OFF instead of half-leaking.

Why is EUV essential around the 7nm node and not before?

Below ~40 nm features, 193 nm deep-UV light needed slow, error-prone multi-patterning; 13.5 nm EUV can resolve those features in a single exposure, which becomes economically necessary at that scale.

Why do modern nodes add more cores instead of raising clock speed?

Because

P_{dyn} \propto f

and heat removal is capped, so pushing

f

hits a thermal wall; spreading work across more cores raises throughput without raising per-transistor switching rate.

Why do we compare MTr/mm² instead of the node name across vendors?

Node names are unstandardized marketing labels, so the same number can mean different real densities; MTr/mm² is a measurable, vendor-neutral quantity that reflects actual scaling.

Why is Backside power delivery introduced around the 2nm generation?

Moving power rails to the wafer's back frees the front metal layers for signal routing and reduces voltage drop, helping density and efficiency once conventional front-side scaling gets crowded.

Edge cases

At exactly 28nm, which transistor architecture is in use, and why is it the last of its kind?

Planar (gate on one face). It's the last long-lived cheap planar node because below it, short-channel leakage forced the switch to three-sided FinFET control.

What happens to leakage in the limiting case where

V_{t h} \to 0

I_{leak} \propto e^{- q V_{t h} / nk T}

approaches its maximum (

e^{0} = 1

factor), so the transistor never fully turns off and static power dominates — the device becomes useless as a switch.

If a "shrink" keeps pitch the same but only renames the node, what happens to density?

Nothing — density

D = N / Area

is unchanged. Density improves only when the actual 2-D pitches shrink (

D_{new} = D_{old} / k^{2}

), not from relabeling.

In the limit

k \to 1

(no real linear shrink), what density gain does a node give?

1/ k^{2} \to 1

, i.e. no density gain. This is the degenerate case where a "new node" is name-only, which is why measured MTr/mm² is the honest check.

Two nodes have identical

α, C, V, f

but node B has much lower

V_{t h}

. Which burns more total power and why?

Node B, despite equal dynamic power, because its lower

V_{t h}

raises

V I_{leak}

exponentially — the static term makes total power higher.

At the FinFET→GAA boundary (~3nm), why do TSMC and Samsung disagree on architecture?

The transition isn't a hard physical wall; TSMC's N3 stayed on FinFET while Samsung moved to GAA, showing the "3nm" label spans different transistor structures — again the label ≠ the physics.

If clock frequency

f

is doubled with everything else fixed, what happens to dynamic power and why is this a wall?

P_{dyn} = α C V^{2} f

doubles; since heat removal is limited, this thermal ceiling is exactly why

f

plateaued rather than continuing to climb with each node.

Recall One-line takeaways

The node number is a label ::: not a physical length since ~22nm. Density is the honest metric ::: compare MTr/mm², scales as $1/ k^{2}$ . Power has two terms ::: $P = α C V^{2} f + V I_{leak}$ . Voltage scaling stopped because ::: lowering $V_{t h}$ causes exponential leakage (Dennard's death). Shape changed, not just size ::: Planar → FinFET → GAA to keep gate control at short channels.