Process nodes (28nm→7nm→5nm→3nm→2nm): Worked examples

Prerequisites we lean on: Dynamic vs static power, Subthreshold leakage, MOSFET threshold voltage, Dennard scaling, Moore's Law. Return to the parent topic any time.

Case class	Which formula	What makes it tricky
A. Normal shrink	$D = D_{o l d} / k^{2}$	plain $k < 1$ , density up
B. Anti-shrink / $k > 1$	$D = D_{o l d} / k^{2}$	features got bigger → density falls
C. Degenerate $k = 1$	$D = D_{o l d} / k^{2}$	"same node rename" → nothing changes
D. Two-axis power	$P_{d y n} = α C V^{2} f$	$C$ and $V$ both move
E. Voltage floor	$V^{2}$ scaling	you can't keep dropping $V$
F. Leakage takeover	$I_{l e ak} \propto e^{- q V_{t h} / nk T}$	exponential beats the $V^{2}$ win
G. Frequency trap	$P_{d y n} \propto f$	smaller node, higher $f$ → power up
H. Real-world word problem	$D$ + die cost	transistors per wafer
I. Exam twist	mixed	"3nm A vs 7nm B" — compare density, not name

Setting a constant we reuse

For the leakage examples we need a number for the "thermal voltage" $k T / q$ . At room temperature (300 K):

Example 1 — Cell A (normal shrink)

Example 2 — Cell B (anti-shrink, $k > 1$ )

Example 3 — Cell C (degenerate $k = 1$ )

Example 4 — Cell D (two-axis power)

Example 5 — Cell E (voltage floor)

Worked example The wall you cannot cross

You want to halve dynamic energy by voltage alone, from $V = 0.90$ V. What $V$ is needed, and why can't you take it?

Forecast: guess the target voltage before computing.

Halving energy means $(V /0.90)^{2} = 0.5$ : $V = 0.90 0.5 \approx 0.636 V .$ Why this step? $P \propto V^{2}$ , so to get factor $0.5$ you take the square root of the voltage ratio — this is why $\cdot$ appears, not linear scaling.
Check against the floor: a transistor still needs $V$ comfortably above $V_{t h} \approx 0.3$ – $0.4$ V to switch fast. $0.636$ V is near the practical floor (~0.7 V for margin). Why this step? The formula gives a number; physics tells us whether the number is allowed. See MOSFET threshold voltage and Dennard scaling.

Verify: $0.63 6^{2} /0.9 0^{2} = 0.404/0.81 = 0.499 \approx 0.5$ . ✓ The take-away: pure voltage scaling runs out of room — leading straight to Example 6.

Example 6 — Cell F (leakage takeover)

Worked example Why lowering voltage further backfires

Push $V_{t h}$ down by $Δ V_{t h} = 0.15$ V (to keep speed at low $V$ ). Using $I_{l e ak} \propto e^{- q V_{t h} / (nk T)}$ with $n = 1.3$ , $k T / q = 0.0259$ V, by what factor does leakage rise? If leakage was 10% of total power before, what is it relative to the old total now?

Forecast: will leakage roughly double, or blow up by 10×+?

The ratio of new to old leakage: since only $V_{t h}$ changed, $\frac{I _{n e w}}{I _{o l d}} = e^{+ q Δ V_{t h} / (nk T)} = exp (\frac{0.15}{1.3 \times 0.0259}) .$ Why this step? Lowering $V_{t h}$ makes the exponent less negative, i.e. multiplies leakage by $e^{+ q Δ V_{t h} / nk T}$ . The $+$ sign is the danger.
Evaluate the exponent: $1.3 \times 0.0259 = 0.03367$ ; $0.15/0.03367 \approx 4.455$ ; so factor $= e^{4.455} \approx 86$ . Why this step? This is the exponential "wall" — a modest 0.15 V drop multiplies leakage ~86×.
Old leakage was 10% of total = $0.10$ (in units of old total). New leakage $\approx 0.10 \times 86 = 8.6$ of the old total. Why this step? Static power now dwarfs the whole old budget — see Dynamic vs static power.

Verify: $exp (0.15/ (1.3 \cdot 0.0259)) = exp (4.455) = 86.0$ ; $0.10 \times 86 = 8.6$ . So the ~49% dynamic saving from Example 4 is annihilated by an 8.6× static blow-up — the derivation-level reason for FinFET/GAA over pure scaling. ✓

Example 7 — Cell G (frequency trap)

Worked example Smaller node, someone cranks the clock

Marketing pairs a node's power win ( $C \to 0.8 C$ , $V : 0.9 \to 0.72$ , giving the $0.512$ factor from Ex. 4) with a 50% higher clock ( $f \to 1.5 f$ ). Net dynamic power vs the old node?

Forecast: still a saving, break-even, or a loss?

$P_{d y n} \propto α C V^{2} f$ ; multiply the Ex.-4 factor by the frequency factor: $\frac{P _{n e w}}{P _{o l d}} = 0.512 \times 1.5 = 0.768.$ Why this step? Frequency enters linearly, so it directly scales whatever the $C V^{2}$ part achieved.
Interpret: only ~23% saved instead of ~49%. Push $f$ to $1.95 \times$ and you'd break even ( $0.512 \times 1.953 = 1.0$ ). Why this step? Shows the exact frequency at which the whole node advantage is eaten — the parent's "smaller node ≠ higher GHz" mistake, quantified.

Verify: $0.512 \times 1.5 = 0.768$ ; break-even $f$ -factor $= 1/0.512 = 1.953$ , and $0.512 \times 1.953 = 1.000$ . ✓

Example 8 — Cell H (real-world word problem, geometric)

Figure — Process nodes (28nm→7nm→5nm→3nm→2nm)

Worked example Transistors per wafer after a shrink

A chip is $10 mm \times 10 mm = 100 mm^{2}$ at $D_{o l d} = 95$ MTr/mm². A shrink $k = 0.75$ keeps the same design (same transistor count) — so the die gets smaller. (a) New die area? (b) How many such dice on a $300$ mm wafer (area $π \cdot 15 0^{2}$ mm², ignore edge waste)? Compare to the old count.

Forecast: roughly how many more dice — 1.3×, 1.8×, or 3×?

Transistor count fixed: $N = 95 \times 100 = 9500$ MTr. New density $D_{n e w} = 95/0.7 5^{2} = 168.9$ MTr/mm². Why this step? Same design means $N$ is the invariant; area is what moves. (Look at the figure: the pink square shrinks to the violet square, same dots inside.)
New die area $= N / D_{n e w} = 9500/168.9 = 56.25 mm^{2}$ . (Check: $100 \times 0.7 5^{2} = 56.25$ ✓ — area shrinks by $k^{2}$ .) Why this step? Two routes to the same area confirm consistency.
Wafer area $= π \times 15 0^{2} = 70686 mm^{2}$ . Old dice $= 70686/100 = 706.9 \to 706$ ; new dice $= 70686/56.25 = 1256.6 \to 1256$ . Why this step? Dice per wafer = usable area ÷ die area; floor because partial dice don't count.

Verify: ratio $1256/706 = 1.779 \approx 1/0.7 5^{2} = 1.778$ — density gain shows up one-to-one as more dice per wafer. ✓ Units: mm²/mm² = pure count. ✓

Example 9 — Cell I (exam twist: name vs density)

Recall Self-test

A node has $k = 0.5$ . Density multiplier? ::: $1/0. 5^{2} = 4 \times$ . Voltage drops $0.9 \to 0.72$ V with $C$ fixed. Dynamic power fraction? ::: $(0.72/0.9)^{2} = 0.64$ . $V_{t h}$ drops 0.15 V, $n = 1.3$ , $k T / q = 26$ mV. Leakage factor? ::: $e^{0.15/ (1.3 \cdot 0.0259)} \approx 86 \times$ . Two chips: 150 vs 120 MTr/mm². Density ratio? ::: $1.25 \times$ — compare density, never the name.

Flashcards

If features get 20% bigger (

k = 1.2

), what happens to density?

It falls by

1/1. 2^{2} = 1.44

⇒ ~30% lower; the

1/ k^{2}

law works both directions.

Why does halving dynamic energy by voltage need

V \to V 0.5

Because

P_{d y n} \propto V^{2}

, so a factor

0.5

in power needs

0.5 \approx 0.707

in voltage.

A node saves 49% dynamic power but clock rises 50%. Net?

0.512 \times 1.5 = 0.768

⇒ only ~23% saved; frequency enters linearly.

Given equal transistor counts, how does dice-per-wafer scale with shrink

k

1/ k^{2}

— die area shrinks as

k^{2}

, so more dice fit in the same wafer area.

Worked examples — Process nodes (28nm→7nm→5nm→3nm→2nm)

The scenario matrix