Process nodes (28nm→7nm→5nm→3nm→2nm): Visual walkthrough

We link the parent Process nodes and prerequisites as we meet them.

Step 1 — What a "pitch" is, and why area is a square

WHAT we do: draw one logic cell as a rectangle whose width $w$ and height $h$ are both set by the pitch $p$ .

WHY: transistors don't float freely — they sit on a grid of wires spaced by $p$ . If wires are $p$ apart, a cell can be no smaller than a few pitches wide and a few pitches tall. So both sides of the rectangle are proportional to $p$ .

PICTURE: look at the blue rectangle below. Its width and height are each some fixed multiple of the pitch $p$ (the orange bar).

The cell area is $A = width \propto p w \times height \propto p h \propto p^{2} .$

Here $A$ is the floor space one transistor cell eats up. The key visual fact: because a rectangle has two sides and both track $p$ , area grows as $p$ squared, not $p$ . That single "squared" is the seed of everything.

Step 2 — Shrink the pitch by a factor $k$ : density doubles

WHAT we do: replace $p$ by $k p$ everywhere and recompute the area.

WHY: a node shrink is not one feature getting smaller — it is the whole grid scaling down together. So both $w$ and $h$ shrink by $k$ .

PICTURE: the two rectangles below are the old cell and the shrunk cell. The new one is $k$ times narrower and $k$ times shorter, so it covers $k^{2}$ of the old floor space.

$A_{new} = (k w) (k h) = both sides shrank k^{2} A_{old} .$

Now define density $D$ = transistors per unit area: $D = \frac{N _{transistors}}{Area} [MTr/mm^{2}] .$

For a fixed die, the number of cells that fit is (die area) $/ A$ . Since $A$ dropped by $k^{2}$ , the count — and hence density — rises by $1/ k^{2}$ : $D_{new} = \frac{D _{old}}{k ^{2}}$

Plug in the classic $k = 0.7$ : $\frac{1}{0. 7 ^{2}} = \frac{1}{0.49} \approx 2$ . A 0.7× linear shrink doubles the transistor count — this is the engine behind Moore's Law.

Step 3 — Where the energy goes: charging one capacitor

WHAT we do: compute the energy to charge $C$ from $0$ V up to the supply voltage $V$ .

WHY a capacitor, and why energy? Every "1→0→1" flip literally fills and empties this capacitor. To know the power we first need the energy per flip, and energy is the natural currency: it is what turns into heat.

PICTURE: the graph below plots charge $q$ on the horizontal axis against voltage $v$ on the vertical. Because $q = C v$ , this is a straight line. The area under it is the stored energy — a triangle.

The energy stored is the triangle's area: $E_{stored} = triangle \frac{1}{2} = C V Q final voltage V = \frac{1}{2} C V^{2} .$

$\frac{1}{2}$ — because voltage rose gradually from 0 to $V$ , so on average you pushed charge against half the final voltage (the triangle, not the full rectangle).
$C$ — how much charge each volt buys.
$V^{2}$ — one $V$ from the charge $Q = C V$ , one $V$ from the voltage it climbed to.

That $V^{2}$ is the second squared in our story, and it is the reason voltage is the most powerful knob we have.

Step 4 — One full switch dissipates $C V^{2}$ , and power is that times frequency

WHAT we do: track one complete cycle — charge up, then discharge — and multiply by how often it happens.

WHY: the stored $\frac{1}{2} C V^{2}$ is not lost; it comes back when the capacitor discharges — but it comes back as heat too. So a full charge-then-discharge cycle burns $\frac{1}{2} C V^{2} + \frac{1}{2} C V^{2} = C V^{2}$ .

PICTURE: the timeline below shows the voltage rising and falling. Each up fills the triangle (heat in the transistor), each down empties it (heat again). Two triangles per cycle = one full $C V^{2}$ .

Now multiply by rate. Let $f$ be the frequency (switch cycles per second) and $α$ the activity factor (the fraction of gates actually flipping each cycle — most sit idle): $P_{dyn} = α C V^{2} f$

$α$ — fraction that are busy (0 to 1); idle gates cost no dynamic energy.
$C$ — smaller transistors ⇒ smaller $C$ , so shrinking helps here too.
$V^{2}$ — the triangle's squared voltage; the biggest lever.
$f$ — cycles per second; doubling clock speed doubles this term.

See Dynamic vs static power for how this pairs with the leakage we build next.

Step 5 — The catch: to stay fast at low $V$ you must lower the threshold

WHAT we do: explain why you can't just lower the supply $V$ for free.

WHY: transistor speed depends on the overdrive $V - V_{t h}$ — how far above threshold you drive it. If you lower $V$ but keep $V_{t h}$ fixed, the overdrive shrinks and the chip slows. To stay fast you must also lower $V_{t h}$ .

PICTURE: the two curves below show drain current vs gate voltage. Lowering the supply $V$ (moving the operating dot left) forces $V_{t h}$ left too, to keep the same overdrive gap.

So far so good — but the next step shows the price of a low $V_{t h}$ .

Step 6 — Leakage: the exponential wall

WHAT we do: write how $I_{leak}$ depends on $V_{t h}$ .

WHY exponential, and why $e$ specifically? The fraction of electrons that have enough thermal energy to hop a barrier of height (energy) $q V_{t h}$ follows a Boltzmann factor — nature's rule that the number able to climb an energy hill falls off as $e^{- energy / k T}$ . The exponential $e^{- x}$ is exactly the tool that answers "what fraction can clear a barrier of height $x$ ?" Nothing else captures that steep collapse.

PICTURE: the curve below plots $I_{leak}$ against $V_{t h}$ on a linear axis. It is a cliff: lower $V_{t h}$ a little and leakage rockets up.

$I_{leak} \propto e^{- q V_{t h} / (nk T)}$

$q$ — charge of one electron (turns a voltage into an energy $q V_{t h}$ ).
$V_{t h}$ — the barrier height in volts; the whole knob we are forced to lower.
$n$ — a fudge factor ( $\approx 1.3$ ) for a non-ideal transistor.
$k$ — Boltzmann's constant; $T$ — temperature. Together $k T$ is the typical thermal energy of an electron.
The minus sign in the exponent: bigger $V_{t h}$ ⇒ fewer electrons clear it ⇒ less leak. So lowering $V_{t h}$ flips that to more leak — exponentially.

Total power is now two pieces: $P = dynamic (Step 4) α C V^{2} f + static leak V I_{leak} .$

See Subthreshold leakage.

Step 7 — The collision: why Dennard scaling broke (~2005)

WHAT we do: overlay the two forces — the $V^{2}$ gain from Step 4 (wants low $V$ ) and the $e^{- q V_{t h} / nk T}$ penalty from Step 6 (punishes low $V_{t h}$ ).

WHY they collide: Step 5 chained them: low $V$ requires low $V_{t h}$ . So the moment you cash in the quadratic dynamic saving, you trip the exponential leakage. Below about $0.7$ V the rising leakage curve overtakes the falling dynamic curve — total power stops dropping and starts rising.

PICTURE: the two curves below cross. The blue dynamic curve falls as $V$ drops; the red leakage curve climbs. Their sum (green) has a minimum near $0.7$ V — you cannot go below it profitably.

This " $V$ won't go below $\sim 0.7$ V" is the whole reason voltage stalled, power density rose, and clock speeds plateaued. See Dennard scaling.

Step 8 — The escape: change the shape, not just the size

WHAT we do: if we can't lower $V_{t h}$ 's leakage penalty by voltage, we lower it by giving the gate more grip on the channel.

WHY: the leakage in Step 6 comes from a channel the gate can't fully shut. Wrap the gate around more sides of the channel and its electric field controls the channel more completely — the "off" state becomes truly off, so we can run at low $V_{t h}$ without the leakage cliff.

PICTURE: three cross-sections — planar (gate on 1 face), FinFET (gate on 3 faces), GAA nanosheet (gate on all 4 faces). More wrap ⇒ more control ⇒ leakage tamed.

Planar (≥28nm): gate on one face — weak control, leaks when short.
FinFET (22nm→7nm): gate on three sides of a raised fin.
GAA nanosheet (3nm, 2nm): gate on all four sides — strongest control.

Printing these tiny shapes needs sharp light: EUV (13.5 nm wavelength) replaced 193 nm deep-UV around 7 nm. Newest nodes also route power from the wafer's back — see Backside power delivery.

The one-picture summary

The single figure above stitches the chain together: squared area ⇒ density $\times 1/ k^{2}$ ; squared voltage ⇒ the tempting dynamic-power lever; exponential leakage ⇒ the wall that stops the lever; and the shape change (FinFET → GAA) that lets us keep going.

Recall Feynman retelling — say it out loud in plain words

Picture a tiny square of silicon. Every transistor sits on a grid, so its floor space is a rectangle whose two sides both track the wire spacing $p$ — that's why area goes as $p$ squared, and shrinking $p$ by $0.7$ doubles how many fit. Now every time a transistor flips, it fills a tiny bucket of charge to voltage $V$ ; the energy is a triangle, $\frac{1}{2} C V^{2}$ , and a fill-then-empty cycle burns $C V^{2}$ , done $f$ times a second for the busy fraction $α$ — that's $α C V^{2} f$ . The juicy trick: since it's $V$ squared, lowering the voltage a little saves a lot. But to stay fast at low $V$ you must lower the turn-on threshold $V_{t h}$ — and a lower barrier lets far more electrons leak over it, following nature's exponential "how many can clear the hill" rule, $e^{- q V_{t h} / nk T}$ . So dropping voltage helps quadratically but hurts exponentially; the two curves cross near $0.7$ V, and that's exactly where voltage — and Dennard scaling — froze around 2005. The fix wasn't a smaller ruler; it was wrapping the gate around more sides of the channel (1 → 3 → 4: planar → FinFET → GAA), so the transistor shuts fully even when tiny. That's what "3nm" and "2nm" really buy: not a 3-nanometre object, but more transistors, cooler switching, and a gate that finally keeps its grip.

Recall Quick self-check

Why does area scale as $k^{2}$ , not $k$ ? ::: A cell is a rectangle; both width and height shrink by $k$ , and area = width × height = $k^{2} \times$ old. Where does the $V^{2}$ in dynamic power come from? ::: Energy to charge a capacitor is the triangle $\frac{1}{2} C V^{2}$ — one $V$ from $Q = C V$ , one $V$ from the voltage climbed. Why can't we just keep lowering $V$ ? ::: To stay fast we must lower $V_{t h}$ too, and leakage $\propto e^{- q V_{t h} / nk T}$ rises exponentially — the leak wall near $0.7$ V. How does GAA dodge that wall? ::: The gate wraps all 4 sides, giving strong enough electrostatic control to run low $V_{t h}$ without runaway leakage.