Process nodes (28nm→7nm→5nm→3nm→2nm): Exercises

Before we start, one reminder of the tools you will reuse (all built in the parent note):

Formula Every equation you need on this page

Density (2-D scaling): $D = \frac{N}{Area} D_{new} = \frac{D _{old}}{k _{shrink}^{2}}$ Capacitance scaling with a shrink (geometry): $C_{new} = k_{shrink} C_{old}$ Dynamic (switching) power: $P_{dyn} = α C V^{2} f$ Static (leakage) power and subthreshold leakage: $P_{static} = V I_{leak} I_{leak} \propto e^{- q V_{t h} / (n k_{B} T)}$

Symbol dictionary — every letter, defined before use:

$D$ = transistor density (transistors per mm², measured in MTr/mm²). $N$ = number of transistors.
$k_{shrink}$ = linear shrink factor per node: how much one length dimension shrinks. $k_{shrink} < 1$ = smaller.
$C$ = load capacitance (charge stored per volt). WHY $C \propto k_{shrink}$ : capacitance grows with the physical size of a device; shrink every length by $k_{shrink}$ and the capacitance falls roughly in the same proportion, so a smaller node helps power for free.
$α$ = activity factor (fraction of time a transistor switches), $V$ = supply voltage, $f$ = clock frequency (switches per second).
$P_{static}$ = static power = the voltage $V$ multiplied by the leakage current $I_{leak}$ (power wasted even when nothing is switching).
$I_{leak}$ = current that dribbles through a transistor that is supposed to be OFF.
$V_{t h}$ = threshold voltage (the gate voltage at which the transistor starts to turn on).
$q$ = the electron charge ( $1.6 \times 1 0^{- 19}$ C), a fixed constant. $n$ = the subthreshold slope factor (a small unitless number, typically 1–1.5, describing how sharply the transistor turns off). $k_{B}$ = Boltzmann's constant. $T$ = absolute temperature in kelvin.
The whole group $n k_{B} T / q$ is just a small voltage (~26 mV at room temperature) that sets how steeply leakage responds to $V_{t h}$ .

See Dennard scaling, Dynamic vs static power, MOSFET threshold voltage, and Subthreshold leakage if any of those symbols feel unfamiliar.

Level 1 — Recognition

L1·Q1

Which of these does the "5" in a "5nm process node" most directly describe today? (a) the physical gate length, (b) the half-pitch, (c) a marketing/generation label, (d) the wafer diameter.

Recall Solution

Answer: (c). Since roughly the 22nm generation the number stopped equalling any single physical feature. At "5nm" the smallest gate is still ≈ 15–20 nm. The number is a generation label; what actually improves is density, power and performance (PPA). (a) and (b) were true historically but not today; (d) is unrelated.

L1·Q2

Put these architectures in the order they appeared as nodes shrank: GAA/nanosheet, Planar, FinFET.

Recall Solution

Planar (≥28nm) → FinFET (22nm–7nm) → GAA/nanosheet (3nm, 2nm). The gate wraps more of the channel each step: one face → three faces → all four faces. See FinFET and GAA transistors.

L1·Q3

State the dynamic-power formula and name every symbol.

Recall Solution

$P_{dyn} = α C V^{2} f$ $α$ = activity factor (fraction of time switching), $C$ = load capacitance, $V$ = supply voltage, $f$ = frequency. The $V^{2}$ comes from the energy $\frac{1}{2} C V^{2}$ stored charging the capacitor plus the same again dissipated discharging → $C V^{2}$ per full cycle.

Level 2 — Application

L2·Q1

A node has density $D_{old} = 60$ MTr/mm². The next node applies a linear shrink of $k_{shrink} = 0.7$ . Estimate the new density.

Recall Solution

WHAT: we scale density by $1/ k_{shrink}^{2}$ . WHY: a cell occupies width × height, both set by pitch; both shrink by $k_{shrink}$ , so area shrinks by $k_{shrink}^{2}$ , so transistors per fixed area rise by $1/ k_{shrink}^{2}$ . $D_{new} = \frac{60}{0. 7 ^{2}} = \frac{60}{0.49} \approx 122.4 MTr/mm^{2} .$ This is the classic ≈ 2× density per node ( $1/0.49 \approx 2.04$ ) behind Moore's Law.

L2·Q2

Node A runs at $V_{A} = 0.9$ V. Node B lowers voltage to $V_{B} = 0.72$ V and cuts capacitance to $C_{B} = 0.8 C_{A}$ . Same $α$ and $f$ . What fraction of Node A's dynamic power does Node B use?

Recall Solution

WHAT: take the ratio $P_{B} / P_{A}$ . WHY we take a ratio, not two full computations: dividing lets the identical, unchanged factors $α$ and $f$ cancel top-and-bottom, so we never need their actual values — only what changed ( $C$ and $V$ ) survives. $\frac{P _{B}}{P _{A}} = \frac{C _{B} V _{B}^{2}}{C _{A} V _{A}^{2}} = 0.8 (\frac{0.72}{0.9})^{2} = 0.8 \times 0.64 = 0.512.$ WHY $(0.72/0.9)^{2} = 0.64$ : $0.72/0.9 = 0.8$ , and squaring $0.8$ gives $0.64$ — the $V$ is squared because energy per switch is $\propto V^{2}$ . Node B uses 51.2% of the power → about a 49% saving. Note the voltage term ( $0.64$ ) does most of the work — that's the power of the $V^{2}$ dependence.

L2·Q3

A chip switches $α = 0.1$ of the time, with $C = 2 pF$ , $V = 0.7$ V, $f = 3 GHz$ . Compute $P_{dyn}$ in watts.

Recall Solution

WHAT: substitute directly into $P_{dyn} = α C V^{2} f$ . WHY no ratio here: we are asked for an absolute wattage, not a comparison, so every symbol must carry its real number and unit. $P_{dyn} = α C V^{2} f = 0.1 \times (2 \times 1 0^{- 12}) \times (0.7)^{2} \times (3 \times 1 0^{9}) .$

$0. 7^{2} = 0.49$ — WHY first: the voltage is the only squared term, so we resolve its square before mixing it with the linear factors, to keep the exponent from wandering onto other symbols.
$0.1 \times 2 \times 1 0^{- 12} = 2 \times 1 0^{- 13}$ — WHY: combine the two pure numbers ( $α$ and $C$ ) first; multiplying small numbers together before the big $f$ keeps the powers of ten easy to track.
$\times 0.49 = 9.8 \times 1 0^{- 14}$ — WHY: now fold in the squared-voltage factor computed above.
$\times 3 \times 1 0^{9} = 2.94 \times 1 0^{- 4}$ W — WHY last: frequency is the largest factor ( $1 0^{9}$ ); doing it last means the exponent bookkeeping ( $1 0^{- 14} \times 1 0^{9} = 1 0^{- 5}$ ) is a single clean step. $P_{dyn} \approx 2.94 \times 1 0^{- 4} W = 0.294 mW .$

Level 3 — Analysis

The figure below is the tool for this level. It plots density $D$ against node step $n$ , starting at $95$ MTr/mm² and applying a $k_{shrink} = 0.7$ shrink at each step, so $D = 95/0. 7^{2 n}$ .

Figure — Process nodes (28nm→7nm→5nm→3nm→2nm)

L3·Q1

Two successive nodes each apply $k_{shrink} = 0.7$ . Starting from $D_{0} = 95$ MTr/mm², find the density after two shrinks. Then report two distinct quantities: (i) the compounded linear length ratio (how short a feature has become), and (ii) the resulting areal density multiplier.

Recall Solution

Each node multiplies density by $1/0. 7^{2}$ . WHY it multiplies (not adds): each shrink acts on the already-shrunk cell, so the factors stack by multiplication — two shrinks give $\frac{1}{0. 7 ^{2}} \times \frac{1}{0. 7 ^{2}} = \frac{1}{0. 7 ^{4}}$ . $D_{2} = \frac{95}{0. 7 ^{2} \cdot 0. 7 ^{2}} = \frac{95}{0. 7 ^{4}} = \frac{95}{0.2401} \approx 395.7 MTr/mm^{2} .$ (i) Compounded linear length ratio (a one-dimensional quantity): each length shrinks by $0.7$ , and two shrinks compound as $0.7 \times 0.7 = 0.49$ — a feature is now 49% as long as it started. This is a length ratio, not an area ratio. (ii) Areal density multiplier (a two-dimensional quantity): because density lives in 2-D, it scales as the square of the inverse length ratio: $1/0.4 9^{2} \approx 4.16$ → roughly 4× density over two generations. WHY keep (i) and (ii) apart: confusing the linear $0.49$ with the areal $4.16$ is the classic linear-vs-areal slip — one is a side length, the other is derived by squaring it. On the s01 figure the $n = 2$ dot sits well above twice the $n = 1$ dot — the tell-tale upward bend of multiplicative growth.

L3·Q2

Subthreshold leakage obeys $I_{leak} \propto e^{- q V_{t h} / (n k_{B} T)}$ (recall $q$ = electron charge, $n$ = subthreshold slope factor, $k_{B}$ = Boltzmann's constant, $T$ = absolute temperature). Suppose lowering $V_{t h}$ makes the exponent increase by $Δ = ln (30)$ . By what factor does leakage rise?

Recall Solution

WHAT tool and WHY: the exponential is chosen because current through an OFF transistor is governed by how many carriers have enough thermal energy to cross the barrier — a Boltzmann factor, which is exponential in the barrier height. The $k_{B} T$ in the denominator is literally the thermal-energy scale; that is why it (not the shrink factor $k_{shrink}$ ) appears here. A change $Δ$ in the exponent multiplies leakage by $e^{Δ}$ . WHY $e^{l n 30} = 30$ : the natural log $ln$ is the inverse of $e^{(\cdot)}$ , so raising $e$ to the power $ln 30$ simply undoes the log and returns $30$ . $\frac{I _{new}}{I _{old}} = e^{l n 30} = 30.$ Leakage rises 30×. This is exactly why you cannot keep lowering $V_{t h}$ (and hence $V$ ) forever — the parent's example 3.

L3·Q3

At $V = 0.7$ V, static (leakage) power is 10% of total; dynamic is 90%. You drop to a lower voltage where leakage rises 30× but dynamic power falls to 0.6 of its old value. Is total power lower or higher? By what factor?

Recall Solution

Take old total $= 1$ unit → old dynamic $= 0.9$ , old static $= 0.1$ (using $P_{static} = V I_{leak}$ for that 10% slice). New dynamic $= 0.6 \times 0.9 = 0.54$ . New static $= 30 \times 0.1 = 3.0$ . $P_{new} = 0.54 + 3.0 = 3.54 units .$ Total power is higher by 3.54× despite the dynamic saving — leakage swamped everything. This is the derivation-level reason nodes changed transistor architecture (FinFET and GAA transistors) instead of only lowering voltage.

Level 4 — Synthesis

L4·Q1

Company X markets "7nm" at 100 MTr/mm². Company Y markets "10nm" at 100 MTr/mm². A student says X's chip is denser because 7 < 10. Evaluate.

Recall Solution

The student is wrong. Node names are not standardized — different companies define them differently. Here both deliver the same 100 MTr/mm², so they are equally dense. The correct comparison metric is always MTr/mm², never the label. (This mirrors the real "Intel 10nm ≈ TSMC 7nm" situation.)

L4·Q2

You want both a 2× density gain and a 40% dynamic-power cut in one node. Density needs $k_{shrink}$ such that $1/ k_{shrink}^{2} = 2$ . Dynamic power, with capacitance scaling as $C_{B} = k_{shrink} C_{A}$ (from the geometry relation $C_{new} = k_{shrink} C_{old}$ in the formula box) and a voltage drop from $0.9$ V to $V_{B}$ , must reach $0.6$ . Find $k_{shrink}$ and the required $V_{B}$ .

Recall Solution

Step 1 — density fixes $k_{shrink}$ . WHY we solve density first: it depends only on $k_{shrink}$ , so it pins down $k_{shrink}$ before power (which needs it) can be tackled. $1/ k_{shrink}^{2} = 2 \Rightarrow k_{shrink}^{2} = 0.5 \Rightarrow k_{shrink} = 0.5 \approx 0.707$ . Step 2 — power. With $C_{B} = k_{shrink} C_{A}$ and same $α, f$ : $\frac{P _{B}}{P _{A}} = k_{shrink} (\frac{V _{B}}{0.9})^{2} = 0.6.$ WHY we isolate $(V_{B} /0.9)^{2}$ : it is the only unknown left, so we divide both sides by the known $k_{shrink}$ to get it alone, then take a square root to peel off the exponent and reach $V_{B}$ . $(\frac{V _{B}}{0.9})^{2} = \frac{0.6}{k _{shrink}} = \frac{0.6}{0.707} = 0.8485$ , so $\frac{V _{B}}{0.9} = 0.8485 = 0.9212$ . $V_{B} = 0.9 \times 0.9212 \approx 0.829 V .$ Interpretation: a modest voltage drop to ≈ 0.83 V, combined with the natural capacitance shrink, meets both targets. Notice how little the voltage had to move — because the $k_{shrink}$ factor from smaller capacitance already helped.

Level 5 — Mastery

L5·Q1

A five-node roadmap applies linear shrink $k_{shrink} = 0.8$ each step for 4 steps (5 nodes total, node 0 → node 4). Node 0 density is 40 MTr/mm². (a) Density at node 4. (b) Overall density multiplier. (c) If Moore's Law wants 2× per node, is $k_{shrink} = 0.8$ enough per node?

Recall Solution

(a) Four shrinks: $D_{4} = \frac{40}{0. 8 ^{2 \cdot 4}} = \frac{40}{0. 8 ^{8}}$ . WHY the exponent is $2 \times 4$ : each of the 4 steps contributes a $1/ k_{shrink}^{2}$ (the "2" from area being two-dimensional), and 4 steps stack multiplicatively → exponent $2 \times 4 = 8$ . Compute $0. 8^{8} = 0.16777$ . So $D_{4} = 40/0.16777 \approx 238.4$ MTr/mm². (b) Multiplier $= 1/0. 8^{8} \approx 5.96 \times$ over four steps. (c) Per node, multiplier $= 1/0. 8^{2} = 1/0.64 \approx 1.5625$ . WHY we compare per-node, not total: Moore's target is stated per generation, so we must isolate one step's factor. Since $1.5625 < 2$ , $k_{shrink} = 0.8$ per node is NOT enough to double each generation — you'd need $k_{shrink} = 1/ 2 \approx 0.707$ for a true 2×. This is one reason pure lithographic shrink alone no longer keeps Moore's Law on pace; design tricks like Backside power delivery and new architectures make up the gap.

L5·Q2

Combine everything. Node old: $V = 0.9$ V, leakage power $= 8%$ of total. Node new applies $k_{shrink} = 0.75$ (so $C \to 0.75 C$ via $C_{new} = k_{shrink} C_{old}$ ), lowers $V$ to $0.75$ V, and — because GAA control improves electrostatics — actually reduces leakage to $0.5 \times$ its old absolute value. Same $α, f$ . Find (a) new dynamic fraction, (b) new total power relative to old.

Recall Solution

Set old total $= 1$ → old dynamic $= 0.92$ , old static $= 0.08$ . (a) New dynamic: scales by $k_{shrink} \cdot (V_{new} / V_{old})^{2} = 0.75 \times (0.75/0.9)^{2}$ . WHY this product: dynamic power $\propto C V^{2}$ ; $C$ shrinks by $k_{shrink} = 0.75$ and $V^{2}$ shrinks by $(0.75/0.9)^{2}$ , so we multiply the two independent scalings. $(0.75/0.9)^{2} = (0.8333)^{2} = 0.6944$ ; $0.75 \times 0.6944 = 0.5208$ . New dynamic $= 0.92 \times 0.5208 = 0.4792$ units. New static: using $P_{static} = V I_{leak}$ with leakage halved → $0.5 \times 0.08 = 0.04$ units. $P_{new} = 0.4792 + 0.04 = 0.5192 units .$ Dynamic fraction of new power $= 0.4792/0.5192 \approx 0.923 = 92.3%$ . (b) Total power $\approx 0.519 \times$ the old → roughly a 48% total-power reduction. WHY this doesn't blow up like L3·Q3: there leakage rose 30×; here GAA lowered leakage to $0.5 \times$ , so the static term shrinks instead of exploding. The architecture change is what makes the voltage drop safe. See FinFET and GAA transistors and MOSFET threshold voltage.

Recall Self-test summary (fill the blanks)

These use the same double-equal cloze markers as the rest of this vault: the highlighted term is what you should recall before revealing. Lines with ::: hide the answer after the colon. Density scales as $D_{new} = D_{old} / == k_{shrink}^{2} ==$ . Dynamic power formula ::: $P_{dyn} = α C V^{2} f$ . Static power formula ::: $P_{static} = V I_{leak}$ . The wall that broke Dennard scaling ::: subthreshold leakage rising exponentially, $I_{leak} \propto e^{- q V_{t h} / (n k_{B} T)}$ (here $k_{B}$ is Boltzmann's constant, not the shrink factor). Correct metric to compare vendors' nodes ::: MTr/mm² (mega-transistors per mm²), not the nm label.