4.3.18 · D1Semiconductor Fabrication

Foundations — Process nodes (28nm→7nm→5nm→3nm→2nm)

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Before you can read a single formula on the parent page, you need a small toolbox of ideas. This page builds every one of them from nothing, in an order where each idea leans only on the ones before it.


0. The picture behind everything: what a transistor is

Every symbol below describes some part of a transistor. So let us draw one first, with zero jargon.

Figure 1 — A transistor is an electric switch. The purple gate on top sits above a teal channel; orange source/drain blocks are the two ends; the black arrow shows current flowing through the channel when the switch is ON.

Figure — Process nodes (28nm→7nm→5nm→3nm→2nm)

The three parts you must be able to name:

Gate
the control terminal; its voltage turns the switch ON or OFF.
Channel
the strip the current flows through when ON.
Source & drain
the two ends current flows between (in through source, out through drain).

1. Length, and the word "pitch"

The oldest meaning of "node" was a length, so we start with length.

Now the word that the node number used to equal:

Figure 2 — Pitch vs. half-pitch. Teal bars are repeated metal lines; the orange double-arrow spans one full wire plus one gap (the pitch ); the plum arrow marks half of it ().

Figure — Process nodes (28nm→7nm→5nm→3nm→2nm)

The "node name" itself


2. Shrink factor — the star of the density story

Because area is a length times a length (a 2-D thing), shrinking each length by shrinks area by . That squared is the single most important idea for "why density doubles."


3. Charge, voltage, capacitance — the power toolbox

Power formulas need three electrical ideas. Build them in order.

Figure 3 — Energy to fill a capacitor is the shaded triangle. As charge grows from to (x-axis), voltage rises linearly from to (y-axis); the orange triangle's area is , the energy stored.

Figure — Process nodes (28nm→7nm→5nm→3nm→2nm)

Now two more symbols, then we turn energy per switch into power:

Frequency
how many times per second a switch could flip (in hertz).
Activity factor
the fraction of switches actually flipping each cycle (between 0 and 1); not every transistor toggles every time.

4. The "OFF isn't really OFF" toolbox — leakage

A perfect switch leaks nothing when OFF. Real transistors do. These symbols describe it.

The parent writes . Decode each new symbol:

the exponential function — the "runaway" curve; a small drop in multiplies leakage many-fold.
the charge of one electron (a fixed constant of nature).
Boltzmann's constant (energy per degree of temperature). We write it not — so it is never confused with the shrink factor of section 2.
absolute temperature (hotter chip = more leakage).
the subthreshold ideality factor. Physically it measures how well the gate voltage reaches the channel: is a perfect gate (all gate voltage controls the channel); means some voltage is "lost" to capacitance in the body, so the switch turns off more sluggishly. Real devices have ; a flat (planar) short transistor has a larger (worse control), which is exactly why leakage got so bad and why FinFET/GAA — which push back toward 1 — were invented.

5. Putting the symbols into "PPA"

Everything above rolls up into the three goals the parent calls PPA (Power, Performance, Area).

Power — the two pieces we just built, added:

Performance — we need a symbol for how fast one switch flips. That time is the gate delay : how long it takes to charge the bucket up to voltage using the transistor's drive (ON) current .

Area / density — the metric that actually improves:


The prerequisite map

nanometre length

pitch and half-pitch

node name meaning

shrink factor k

area scales as k squared

density D

voltage V

power equals I times V

capacitance C and charge Q

dynamic power

frequency f

activity factor

threshold voltage

leakage exponential

temperature T

static power

gate delay and fmax

Power Performance Area

Process nodes 28nm to 2nm

Every arrow means "you must understand the source before the target makes sense." The whole map funnels into the parent topic: the process-nodes topic.


Equipment checklist

Test yourself — cover the right side and answer before revealing.

How big is in metres, and roughly how many atoms wide is "5nm"?
; about 25 atoms.
What does pitch measure (vs. wire width)?
Centre-to-centre distance of repeated lines = one wire plus one gap.
What does a modern node name ("5nm") actually denote?
A manufacturing generation label, decoupled from any real dimension; compare by density instead.
Why is the shrink factor always less than 1?
Because a new node makes lengths smaller, so new/old < 1.
Why does area scale as and not ?
Area is length × length (2-D), so each factor of appears twice.
State the relation between charge, capacitance and voltage.
.
State the basic power law linking current and voltage.
(push times flow = energy per second).
Where does the in dynamic power come from?
Energy to fill a capacitor is ; charging + discharging costs per switch.
Turn energy-per-switch into dynamic power.
Multiply by real switches per second : .
Why is static power written ?
Because ; the supply voltage is applied while leakage current trickles, even when OFF.
What is , and why can't we drop it freely?
The gate voltage where the switch turns ON; lowering it raises leakage exponentially.
What does the ideality factor mean, and its typical range?
How well the gate voltage reaches the channel; is perfect, real devices ; larger = worse control = more leakage.
Why is Boltzmann's constant written here, not ?
To avoid clashing with the shrink factor from section 2.
Give the gate-delay estimate and the resulting .
, so .
Define density , including what is.
in MTr/mm², where is the count of transistors in that area.