Power gating and clock gating

Overview

Modern chips burn power even when idle. Power gating and clock gating are two fundamental techniques to reduce dynamic power and static power in digital circuits, critical for battery life, thermal limits, and data-center energy costs.

Clock Gating

What It Is

Clock gating disables the clock signal to a circuit block when that block is not performing useful work. The combinational logic still has power, but flip-flops don't toggle, so no dynamic power is burned by charging/discharging their internal capacitances.

Why Dynamic Power Depends on Clock Toggles

Recall dynamic power:

When a flip-flop's clock input toggles, internal nodes charge/discharge even if the data input doesn't change. By stopping the clock ( $\alpha \to 0$ for that block), we eliminate those transitions.

How Clock Gating Works (Derivation)

Original circuit: Clock reaches every flip-flop unconditionally.
Insert a clock gate: An AND gate combines the global clock with an enable signal: $\text{gated\_clk} = \text{clk} \land \text{enable}$
When enable = 0: gated_clk stays constant (low), flip-flops hold their state, no dynamic power.
When enable = 1: gated_clk follows the clock, circuit operates normally.

Why this works: Flip-flops only consume dynamic power when their clock input toggles. A constant clock → no transitions → $\alpha = 0$ for that block.

Worked example Clock Gating a Register File

Scenario: An 8-register file in a CPU. Instructions only read/write registers 20% of the time. Without clock gating:

All 8 registers clock every cycle.
$P_{\text{dyn}} = \alpha \, C \, V^2 \, f$ with $\alpha \approx 0.5$ (typical toggle rate). With clock gating:
Enable signal = register_access (high only during load/store).
Clock runs 20% of cycles: effective $\alpha_{\text{eff}} = 0.5 \times 0.2 = 0.1$ .
Power savings: $\frac{0.5 - 0.1}{0.5} = 80\%$ dynamic power in that block.

Why this step? The register file's enable is derived from the instruction decoder. When no register op is decoded, enable = 0, and the clock gate holds the register file's clock low.

Worked example Latch-Based Clock Gating (Glitch-Free)

Problem: Naive AND gate can create glitches if enable changes while clk = 1.

Solution: Insert a latch to hold enable stable:

Latch samples enable on the negative edge of clk.
Latched enable feeds the AND gate.
Enable only changes when clk = 0, so AND output is glitch-free.

Circuit:

clk ----+----AND----> gated_clk
        |     
     LATCH----+
        |
     enable

Why this step? If enable goes low during clk = 1, the AND gate's output drops mid-cycle, creating a spurious clock edge. The latch ensures enable is stable when clk = 1, preventing false triggers.

Power Gating

What It Is

Power gating completely shuts off power supply ( $V_{\text{dd}}$ ) to a circuit block using header or footer switches (large PMOS/NMOS transistors). This eliminates both dynamic power and static leakage power.

Why Static Power Matters

Even when a circuit is idle (clock gated), subthreshold leakage and gate leakage in transistors cause static power:

Clock gating does not stop leakage because $V_{\text{dd}}$ is still applied. Power gating cuts $V_{\text{dd}}$ , so $I_{\text{leak}} \to 0$ .

How Power Gating Works (Derivation)

Insert a power switch: A PMOS transistor (header switch) between $V_{\text{dd}}$ and the block, or NMOS (footer switch) between block and ground.
Control signal: A sleep signal drives the switch gate.
- sleep = 0: Switch ON, block powered.
- sleep = 1: Switch OFF, block isolated, leakage ≈ 0.
State retention: Registers lose their values when powered down. Use retention flip-flops (slave latch powered by an always-on rail) or save state to memory before shutdown.

Why this works: With $V_{\text{dd}}$ disconnected, no voltage across transistors → no leakage paths → $P_{\text{static}} \to 0$ .

Worked example Power Gating a GPU Shader Core

Scenario: A GPU with 32 shader cores. Gaming workload uses 8 cores; other 24 are idle.

Without power gating:

24 idle cores leak current: $P_{\text{leak}} = 24 \times 50\,\text{mW} = 1.2\,\text{W}$ . With power gating:
Turn off 24 cores using header switches.
Leakage drops to ~0.01 W (switch leakage only).
Savings: ~1.19 W.

Wake-up penalty: When a core is needed again:

De-assert sleep → power switch turns on (10-100 ns).
Restore pipeline state from retention registers (another 100ns).
Total wake-up latency: ~200 ns. Why this step? The OS/driver predicts idle periods (e.g., frame render finished, no work for 5 ms). If idle time > wake-up time, power gating saves energy. Trade-off: latency vs. energy.

Comparison Table

Feature	Clock Gating	Power Gating
Targets	Dynamic power ( $\alpha C V^2 f$ )	Dynamic + Static power
Mechanism	Disable clock to flip-flops	Disconnect $V_{\text{dd}}$ via switch
State retention	Automatic (flip-flops hold state)	Requires retention cells or save/restore
Wake-up latency	0 cycles (instant)	10s-100s of ns (switch + restore)
Area overhead	Small (AND gates + latch)	Moderate (large power switches + retention)
Leakage reduction	None	~99%
Use case	Short idle periods (μs)	Long idle periods (ms+)

Common Mistakes

Derivation from First Principles: Power Gating Savings

Goal: Quantify energy saved by power-gating a block for time $T_{\text{sleep}}$ .

Without power gating:

Dynamic power: $P_{\text{dyn}} = \alpha C V^2 f$ (but $\alpha = 0$ if clock-gated).
Static power: $P_{\text{static}} = I_{\text{leak}} V_{\text{dd}}$ .
Energy over $T_{\text{sleep}}$ : $E_{\text{no\_pg}} = P_{\text{static}} \, T_{\text{sleep}}$ .

With power gating:

Turn off at $t = 0$ , wake at $t = T_{\text{sleep}}$ .
During sleep: $P \approx 0$ (only switch leakage, ~1% of $P_{\text{static}}$ ).
Wake-up energy: $E_{\text{wake}} = C_{\text{block}} V_{\text{dd}}^2$ (recharge all gates).
Total energy: $E_{\text{pg}} = E_{\text{wake}} + 0.01 \, P_{\text{static}} \, T_{\text{sleep}}$ .

Savings condition: $E_{\text{no\_pg}} > E_{\text{pg}}$ $P_{\text{static}} \, T_{\text{sleep}} > C_{\text{block}} V_{\text{dd}}^2 + 0.01 \, P_{\text{static}} \, T_{\text{sleep}}$ $0.99 \, P_{\text{static}} \, T_{\text{sleep}} > C_{\text{block}} V_{\text{dd}}^2$ $T_{\text{sleep}} > \frac{C_{\text{block}} V_{\text{dd}}^2}{0.99 \, P_{\text{static}}}$

Define break-even time $T_{\text{BE}}$ :

Example numbers:

$C_{\text{block}} = 1\,\text{nF}$ (a shader core).
$V_{\text{dd}} = 1\,\text{V}$ .
$P_{\text{static}} = 50\,\text{mW}$ .
$T_{\text{BE}} = \frac{10^{-9} \times 1^2}{0.05} = 20\,\text{ns}$ .

Why this step? If the block is idle for > 20 ns, power gating wins. Shorter idles waste energy on wake-up. Modern power management controllers predict idle durations to decide gating policy.

Recall Feynman Explanation (ELI12)

Imagine your house has20 rooms, but you only use 3 rooms today. Leaving lights on in all 20 rooms wastes electricity, right?

Clock gating is like turning off the light switch in the17 empty rooms. The electricity is still connected to those rooms, but the bulbs aren't flashing on and off, so you don't waste power on the flashing part. But the wires still leak a tiny bit of electricity (like a phone charger that's pluged in but not charging—still warm).

Power gating is like unplugging those 17 rooms from the main power box. Now there's no electricity at all—no flashing, no leaking. But when you need a room again, you have to walk to the power box and flip the breaker back on, which takes a few seconds. If you need the room again in 10 seconds, it's not worth unplugging.

The trick: Use light switches (clock gating) for quick breaks (lunch), and unplug (power gating) for long vacations (overnight).

Connections

Dynamic and Static Power—Clock gating targets $\alpha$ in $P_{\text{dyn}}$ ; power gating eliminates $P_{\text{static}}$ .
Subthreshold Leakage—Why power gating is critical below 45nm nodes.
Retention Flip-Flops—How to preserve state across power-gating.
DVFS (Dynamic Voltage and Frequency Scaling)—Often combined with gating for maximum savings.
Multi-Threshold CMOS—Another technique to reduce leakage (high- $V_t$ transistors for power switches).
Hierarchical Clock Distribution—Where to insert clock gates (local vs. global).
Power Management IC (PMIC)—External controller that orchestrates gating policies.

Active Recall Flashcards

#flashcards/hardware

What is clock gating? :: Disabling the clock signal to a circuit block when idle, using AND gates, to eliminate dynamic power from flip-flop toggles while keeping logic powered.

What is power gating?

Disconnecting Vdd or ground from a circuit block via header/footer switches to eliminate both dynamic and static (leakage) power, with state loss unless retention cells are used.

Why does clock gating NOT reduce leakage power?

Because Vdd remains connected to the transistors, so subthreshold and gate leakage currents still flow even when the clock is stopped.

What is the break-even time for power gating?

The minimum idle duration

T_{\text{BE}} = \frac{C_{\text{block}} V_{\text{dd}}^2}{P_{\text{static}}}

for which the energy saved by eliminating leakage exceeds the energy cost of waking the block back up.

What is a retention flip-flop?

A flip-flop with a slave latch powered by an always-on Vret rail, so it retains 1 bit of state when the main power domain is gated off.

Why use a latch in clock gating?

To prevent glitches: the latch samples the enable signal on the clock's negative edge, ensuring enable is stable when clk = 1, avoiding false clock edges from enable transitions.

Clock gating reduces __ power, power gating reduces ___ power.

dynamic; static (leakage)

What is the wake-up latency trade-off for power gating?

Power gating has10-100 ns wake-up delay (switch on + state restore), so it's only beneficial if idle time exceds this delay; clock gating has zero latency.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, chip ke andar millions of transistors hote hain, aur inko chalane mein power lagti hai. Problem yeh hai ki bahut saare parts — jaise GPU shaders, ALUs, memory controllers — zyada time idle rehte hain, phir bhi power khaate rehte hain. Yahi cheez battery life kharab karti hai aur chip garam karti hai. Toh core intuition simple hai: jo block kaam nahi kar raha, uski clock ya power band kar do, jisse energy bache bina functionality lose kiye. Do main techniques hain — clock gating aur power gating.

Clock gating mein hum clock signal ko idle block tak jaane se rokte hain ek AND gate laga ke, jahan gated_clk = clk AND enable. Jab enable = 0, clock constant reheta hai, toh flip-flops toggle nahi karte, aur dynamic power (yaad rakho formula: P = α·C·V²·f) mein activity factor α zero ho jaata hai. Matlab clock hi nahi toggle karega toh capacitance charge-discharge nahi hoga, aur power bach jaayegi. Ek register file example mein, agar sirf 20% time register access hota hai, toh clock gating se 80% tak dynamic power save ho sakti hai! Bas ek dhyaan dene wali baat — glitch avoid karne ke liye ek latch lagate hain jo enable ko clk ke negative edge pe stable rakhta hai, taaki koi galat clock edge na bane.

Power gating thoda aur aggressive hai — yeh poora power supply (Vdd) hi cut kar deta hai header ya footer switches (bade PMOS/NMOS transistors) use karke. Isse dynamic power ke saath-saath static leakage power bhi khatam ho jaati hai, jo clock gating nahi kar paata. Yeh why-it-matters isliye hai kyunki aaj ke smartphones, laptops aur data-centers mein energy efficiency sabse bada concern hai — thoda sa power save karna matlab lambi battery life, kam heat, aur crores ka bijli bill bachana. Toh ye techniques modern hardware design ki backbone hain, aur inko samajhna tumhe efficient chip design ki foundation dega.

Overview

Clock Gating

What It Is

Why Dynamic Power Depends on Clock Toggles

How Clock Gating Works (Derivation)

Power Gating

What It Is

Why Static Power Matters

How Power Gating Works (Derivation)

Comparison Table

Common Mistakes

Derivation from First Principles: Power Gating Savings

Connections

Active Recall Flashcards

Concept Map

Hinglish (regional understanding)

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Power, Thermal & Reliability

Connections