Visual walkthrough — Power gating and clock gating

This page builds the central result of the parent topic from the ground up: where a chip's power actually goes, and exactly how gating shrinks it. We will use pictures for every step. No symbol appears before we draw it.

Let us start by agreeing on a single number we want to make small: the power a block of logic burns.

---

Step 1 — What "power" even means here

WHAT. A chip block is a bag of tiny switches (transistors) fed by a voltage rail. "Power" is simply how fast it drains energy, measured in watts (joules per second). We split it into two piles:

WHY split them? Because the two gating techniques attack different piles. If you don't know which pile is bigger, you can't pick the right tool. (More on the piles in Dynamic and Static Power.)

PICTURE. Two stacked bars: the "moving charge" pile on top, the "quiet leak" pile at the bottom. Everything on this page is about shrinking one or both bars.

---

Step 2 — Why moving charge costs energy (the capacitor)

WHAT. Every wire and gate input behaves like a capacitor: a bucket that must be filled with charge to read as "1" and emptied to read as "0". Call the size of that bucket $C$ (its capacitance) and the rail voltage $V_{\text{dd}}$.

WHY a capacitor and not something simpler? Because charge doesn't teleport. To raise a wire to $V_{\text{dd}}$ you push charge $Q=C{V}_{\text{dd}}$ into it, and pushing charge across a voltage costs energy. This is the physical reason flipping a bit is never free.

PICTURE. A bucket labelled $C$ under a tap at height $V_{\text{dd}}$: filling it (orange) then dumping it (blue). One fill+dump = one $E_{\text{cycle}}$.

---

Step 3 — From one flip to a stream of flips: dynamic power

WHAT. Real circuits flip many times per second. The clock ticks $f$ times a second (its frequency), and only a fraction $\alpha$ of the buckets actually flip on any given tick.

WHY introduce $\alpha$ and $f$? Power is energy per second. So we multiply the energy of one flip by how many flips happen per second. $f$ counts ticks; $\alpha$ (the activity factor) accounts for the fact that not every bucket flips every tick.

Key observation for later: if we can force $\alpha \to 0$, then $P_{\text{dyn}}\to 0$ no matter how big $C$, $V_{\text{dd}}$, or $f$ are. This is the seed of clock gating.

PICTURE. A row of buckets under a ticking clock; only the fraction $\alpha$ light up (flip) each tick. Fewer lit buckets = shorter bar.

---

Step 4 — Clock gating: choke $\alpha$ to zero

WHAT. A flip-flop only flips its internal nodes when its clock input toggles. So put a gate on the clock wire: an AND of the real clock with an enable line.

$\text{gated\_clk}=\text{clk}\wedge \text{enable}$

• $\wedge$ — logical AND: output is 1 only if both inputs are 1
• when enable = 1: gated_clk copies clk (ticks pass through) → block runs normally
• when enable = 0: gated_clk is stuck low (flat line) → clock stops toggling → $\alpha =0$

WHY AND, and why the clock line? The clock is the source of every flip in synchronous logic. Kill the clock's toggling and every downstream bucket freezes — you disable the whole block with one gate. AND is the natural "pass-through only when allowed" gate.

PICTURE. Left half: enable = 1, the gated clock is a clean square wave. Right half: enable = 0, the gated clock goes flat. The frozen region has $\alpha =0$.

See Hierarchical Clock Distribution for where these enables sit in the clock tree.

---

Step 5 — The glitch trap (a degenerate case)

WHAT. A naive AND has a hidden failure. If enable drops from 1 to 0 while clk is still high, the AND output falls mid-pulse. That short flat-then-fall looks like an extra clock edge — a glitch — and can wrongly trigger a flip-flop.

WHY it fails. The AND obeys its inputs instantly. It has no idea that a "1" already in flight should be finished. So a mid-pulse enable change corrupts the pulse shape.

FIX. Insert a latch that samples enable on the clock's falling edge, so the AND only ever sees an enable that changed while clk = 0. Now enable is guaranteed stable during the high phase → no glitch.

PICTURE. Top trace: raw enable falling mid-high — the AND produces a jagged glitch (red). Bottom trace: latched enable, which only moves while clk is low — clean pulses (green).

---

Step 6 — Why clock gating leaves a bar behind: leakage

WHAT. Freeze the clock and $P_{\text{dyn}}=0$ — but the bottom bar from Step 1 survives. As long as $V_{\text{dd}}$ is connected, transistors leak a small subthreshold current $I_{\text{leak}}$ even when "off".

WHY it matters now. In deep-submicron nodes (7 nm), this trickle can be 30–40% of total power. Clock gating never touches it — because $V_{\text{dd}}$ is still there. To kill leakage you must attack $V_{\text{dd}}$ itself.

PICTURE. The Step-1 bar chart repeated three times: full block; clock-gated (top pile gone, bottom pile remains); the arrow points at the stubborn bottom bar we still need to remove.

---

Step 7 — Power gating: cut the rail itself

WHAT. Put a big transistor switch in series with the rail. A PMOS above the block is a header switch; an NMOS below is a footer switch. A sleep signal opens it.

• sleep = 0 → switch closed → block sees $V_{\text{dd}}$ → runs normally
• sleep = 1 → switch open → block disconnected → voltage across it collapses → $I_{\text{leak}}\to 0$

WHY this works. Leakage needs a voltage to push it. Remove the voltage (open the rail) and both piles vanish: no dynamic power (no rail to swing) and no static power (no rail to leak from). This is why power gating is strictly more powerful — and strictly more disruptive — than clock gating. It relates to Multi-Threshold CMOS, where these switches use high-threshold transistors that themselves barely leak.

PICTURE. The rail with a header switch drawn as a gate. Left: closed, block powered (green). Right: open, block dark, a tiny residual switch leak only.

---

Step 8 — The cost: state loss and wake-up (edge case)

WHAT. Cut $V_{\text{dd}}$ and every ordinary flip-flop forgets its bit. And turning the rail back on isn't instant: the big switch takes time to charge the block's buckets, then state must be restored.

Two remedies:

1. Save/restore the state to always-on memory before sleeping.
2. Retention flip-flops — a slave latch on a tiny always-on rail $V_{\text{ret}}$ holds one bit through the sleep (see Retention Flip-Flops).

WHY this is the deciding trade-off. Power gating pays a wake-up latency (roughly 10–100 ns for the switch plus ~100 ns to restore, ≈200 ns total). It only wins if the idle time is longer than that latency. Predicting idle length is a job for the OS, DVFS (Dynamic Voltage and Frequency Scaling) controller, or the Power Management IC (PMIC).

PICTURE. A timeline: block active, then sleep asserted (dark), then wake-up ramp (orange) before active again. A green "save" tick before sleep and a green "restore" tick after wake.

---

The one-picture summary

This final figure compresses the whole walkthrough: the two power piles from Step 1, and where each technique cuts. Clock gating slices the dynamic pile (via $\alpha \to 0$); power gating slices both piles (via $V_{\text{dd}}\to 0$) at the price of wake-up time.

Recall Feynman retelling — say it plainly

A chip wastes power two ways. One: every time a wire flips, you fill and dump a little bucket of charge — that's dynamic power, and it scales with how often things flip. Two: even when nothing flips, a tiny current leaks through the transistors as long as the wall socket ($V_{\text{dd}}$) is plugged in — that's static power.

Clock gating is like pausing the metronome for a band that's resting: stop the clock ticks and the flip-flops stop flipping, so the flipping-bucket cost drops to zero. But the amp is still plugged in — leakage keeps trickling. Cheap, instant, no memory loss, great for short breaks. Just remember the latch, or you'll create a fake beat (glitch) and confuse the band.

Power gating is unplugging the amp entirely: no rail, so nothing flips and nothing leaks — both bars gone. But the band forgets its sheet music (state loss), and plugging back in and re-reading the music takes real time (wake-up ~200 ns). So you only unplug when the break is long enough to be worth it, and you keep the sheet music safe in a retention latch on a tiny always-on rail.

One sentence: choke $\alpha$ for short idles, kill $V_{\text{dd}}$ for long ones.

Recall Quick self-test

What does clock gating drive to zero, and which power pile survives? ::: It drives the activity factor $\alpha \to 0$, killing dynamic power; the static leakage pile survives because $V_{\text{dd}}$ is still connected. Why is a bare-AND clock gate dangerous? ::: If enable changes while clk is high, the AND output falls mid-pulse, creating a glitch (a false clock edge); a falling-edge latch fixes it. Register file used 20% of cycles, ungated $\alpha =0.5$ — dynamic power saved? ::: ${\alpha }_{\text{eff}}=0.5\times 0.2=0.1$, so $(0.5-0.1)/0.5=80\%$ saved. Why does power gating need retention flip-flops? ::: Cutting $V_{\text{dd}}$ erases ordinary flip-flops; a slave latch on an always-on $V_{\text{ret}}$ rail preserves the bit across sleep.

---

Where this connects