Power gating and clock gating: Worked examples — Hardware deep dive

This page is a workbook. We take the ideas from the parent note and grind them through every kind of number you could meet: normal cases, zero/degenerate inputs, the break-even limit, a word problem, and an exam twist. Guess first, then check.

Everything here rests on three formulas the parent built. Before we use any symbol, here it is in plain words:

See Dynamic and Static Power and Subthreshold Leakage for where these come from.

The scenario matrix

Every worked example below is tagged with the matrix cell it lands in. Read this table first — it is the map.

Cell	Case class	What makes it tricky	Example
A	Ordinary clock-gate saving	plug-and-chug $α$ reduction	Ex 1
B	Zero / degenerate input	block always active ( $α_{eff} = α$ ) → savings = 0	Ex 2
C	Static vs dynamic split	clock gating leaves leakage untouched	Ex 3
D	Power-gate energy break-even	the wake-up limit $t_{idle} = t_{BE}$	Ex 4
E	Below the limit (idle too short)	power gating loses — negative saving	Ex 5
F	Real-world word problem	multi-core GPU, combine leakage + wake-up	Ex 6
G	Combined clock+power gating	two techniques stacked	Ex 7
H	Exam-style twist	DVFS changes $V_{dd}$ and $f$ at once	Ex 8

Every numeric answer on this page is machine-checked in the Verify block.

Ex 1 — Cell A: the ordinary clock-gate saving

Worked example Statement

A register file toggles with $α = 0.5$ normally. Clock gating enables it only 20% of cycles. By what percentage does dynamic power in that block drop?

Forecast: Guess the drop before reading — is it 20%, 80%, or something else?

Find the effective activity. When the clock only runs 20% of cycles, the block only switches 20% as often: $α_{eff} = α \times 0.20 = 0.5 \times 0.20 = 0.1$ Why this step? Dynamic power is linear in $α$ (look at the formula — $α$ sits out front, not squared). Cutting how often the clock ticks cuts $α$ by the same fraction.
Take the ratio of powers. All other terms ( $C, V_{dd}^{2}, f$ ) are identical gated vs ungated, so they cancel: $\frac{P _{gated}}{P _{ungated}} = \frac{α _{eff}}{α} = \frac{0.1}{0.5} = 0.2$ Why this step? We only care about the change, so dividing kills every unchanged factor — no need to know $C$ or $V_{dd}$ .
Convert to a saving. $saving = 1 - 0.2 = 0.8 = 80%$ Why this step? "Saving" is the fraction we removed, which is one minus what remains.

Verify: $80%$ saving means $20%$ remains; $20%$ of the original activity is exactly the $0.1$ we computed. Units: all dimensionless ratios — consistent. ✓

Ex 2 — Cell B: the degenerate case (nothing to gate)

Ex 3 — Cell C: clock gating does nothing for leakage

Worked example Statement

An idle ALU is clock-gated. It has $I_{leak} = 2 mA$ at $V_{dd} = 0.9 V$ . How much static power still burns while it "sleeps" under clock gating alone?

Forecast: Should clock gating drive this to zero?

Recall what clock gating touches. It freezes the clock, so $α \to 0$ and $P_{dyn} \to 0$ . But $V_{dd}$ is still connected. Why this step? The leakage path exists whenever voltage sits across a transistor — the clock is irrelevant to it (see Subthreshold Leakage).
Compute the surviving static power. $P_{static} = I_{leak} V_{dd} = 2 \times 1 0^{- 3} A \times 0.9 V = 1.8 \times 1 0^{- 3} W = 1.8 mW$ Why this step? This is exactly the number clock gating cannot remove — the argument for Multi-Threshold CMOS and power gating.

Verify: Units $A \times V = W$ . ✓ The block still leaks $1.8 mW$ ; only power gating (cutting $V_{dd}$ ) kills it.

Ex 4 — Cell D: the power-gate break-even limit

This is the most important calculation on the page: when is power gating worth it? It gets a figure.

Ex 5 — Cell E: below the limit — power gating LOSES

Ex 6 — Cell F: the GPU word problem

Worked example Statement

A GPU has 32 shader cores; a game uses 8, leaving 24 idle. Each core leaks $50 mW$ at $0.9 V$ ; power-gated switch leakage is $\approx 0.4 mW$ per core. Idle windows are $5 ms$ between frames, and each wake costs $8 μ J$ . (a) Leakage saved? (b) Is 5 ms past break-even?

Forecast: Roughly how many watts, and comfortably past break-even?

Leakage before gating (24 cores). $P_{before} = 24 \times 50 mW = 1200 mW = 1.2 W$ Why this step? Idle cores leak independently, so total = per-core × count.
Leakage after gating. $P_{after} = 24 \times 0.4 mW = 9.6 mW$ Why this step? Cutting $V_{dd}$ leaves only tiny switch leakage — not exactly zero, so we keep the residual term.
Saved power. $P_{save} = 1200 - 9.6 = 1190.4 mW \approx 1.19 W$
Per-core break-even, then compare 5 ms. $t_{BE} = \frac{E _{wake}}{P _{save,core}} = \frac{8 \times 1 0 ^{- 6} J}{( 50 - 0.4 ) \times 1 0 ^{- 3} W} = 1.613 \times 1 0^{- 4} s \approx 161 μ s$ Why this step? Break-even is per core (each wakes independently). $5 ms = 5000 μ s ≫ 161 μ s$ , so gate them.

Verify: $1.19 W$ matches the parent note's GPU figure. $5000/161 \approx 31 \times$ the break-even — deep in the winning region. ✓ A Power Management IC (PMIC) plus the driver schedules this.

Ex 7 — Cell G: stacking clock + power gating

Worked example Statement

A block runs at $α = 0.4$ , $C = 2 nF$ , $V_{dd} = 1.0 V$ , $f = 1 GHz$ , and leaks $I_{leak} = 3 mA$ . Compare total power in three states: (i) active, (ii) clock-gated, (iii) power-gated (assume leakage $\to 0$ ).

Forecast: Which state wins, and does clock gating remove all the idle power?

Active dynamic power. $P_{dyn} = α C V_{dd}^{2} f = 0.4 \times 2 \times 1 0^{- 9} \times 1. 0^{2} \times 1 \times 1 0^{9} = 0.8 W$
Active static power. $P_{static} = I_{leak} V_{dd} = 3 \times 1 0^{- 3} \times 1.0 = 3 \times 1 0^{- 3} W = 3 mW$ Active total $= 0.8 + 0.003 = 0.803 W$ .
Clock-gated: $P_{dyn} \to 0$ , but leakage stays. $P_{clk-gated} = 0 + 3 mW = 3 mW$ Why this step? Cell C's lesson in action — clock gating cannot touch the $3 mW$ .
Power-gated: both terms vanish. $P_{pwr-gated} \approx 0 W$

Verify: Ordering $0.803 W > 3 mW > 0$ . Clock gating removes the $0.8 W$ dynamic part (the big one), power gating removes the last $3 mW$ . For a long idle, power-gate; for a short one, clock-gate. ✓

Ex 8 — Cell H: the exam twist (DVFS changes V and f together)

Worked example Statement

A block runs at $V_{dd} = 1.0 V$ , $f = 1 GHz$ . DVFS scales it to $V_{dd} = 0.8 V$ , $f = 0.7 GHz$ (same $α, C$ ). By what fraction does dynamic power drop?

Forecast: The trap: does power scale like $0.8 \times 0.7$ ? Careful — voltage is squared.

Write the ratio, keep only what changed. $\frac{P _{new}}{P _{old}} = \frac{V _{new}^{2} f _{new}}{V _{old}^{2} f _{old}}$ Why this step? $α$ and $C$ are unchanged, so they cancel; only $V^{2}$ and $f$ survive.
Plug in — and square the voltage. $= \frac{0. 8 ^{2} \times 0.7}{1. 0 ^{2} \times 1.0} = \frac{0.64 \times 0.7}{1} = 0.448$ Why this step? The squared voltage is why DVFS is so powerful: a 20% voltage cut alone gives $0. 8^{2} = 0.64$ , a 36% power drop before frequency even helps.
Saving. $1 - 0.448 = 0.552 = 55.2%$

Verify: Naive (un-squared) guess would be $0.8 \times 0.7 = 0.56 \Rightarrow 44%$ saving — wrong. The correct $55.2%$ is larger precisely because voltage enters squared. This is the exam trap. ✓

Recall Quick self-test

Power gating on a $30 μ s$ idle when $t_{BE} = 100 μ s$ — good idea? ::: No — idle is below break-even; use clock gating (Cell E). Clock gating drops leakage to zero? ::: No — leakage needs $V_{dd}$ cut, i.e. power gating (Cell C). DVFS from $1.0 V$ to $0.8 V$ (same $f$ ) — dynamic power ratio? ::: $0. 8^{2} = 0.64$ .