Power gating and clock gating: Worked examples — Hinglish deep dive

6.4.4 · D3 · Hardware › Power, Thermal & Reliability › Power gating and clock gating

Yeh page ek workbook hai. Hum parent note ke ideas lete hain aur unhe har tarah ke numbers ke through grind karte hain: normal cases, zero/degenerate inputs, break-even limit, ek word problem, aur ek exam twist. Pehle guess karo, phir check karo.

Yahan sab kuch teen formulas par tikaa hai jo parent ne build ki thi. Koi bhi symbol use karne se pehle, yeh raha plain words mein:

Yeh kahan se aate hain, yeh jaanne ke liye Dynamic and Static Power aur Subthreshold Leakage dekho.

Scenario matrix

Neeche har worked example ko us matrix cell ke saath tag kiya gaya hai jisme woh fit hota hai. Pehle yeh table padho — yeh map hai.

Cell	Case class	Kya cheez tricky banati hai	Example
A	Ordinary clock-gate saving	plug-and-chug $α$ reduction	Ex 1
B	Zero / degenerate input	block hamesha active ( $α_{eff} = α$ ) → savings = 0	Ex 2
C	Static vs dynamic split	clock gating leakage ko untouched chodta hai	Ex 3
D	Power-gate energy break-even	wake-up limit $t_{idle} = t_{BE}$	Ex 4
E	Limit se neeche (idle bahut chhota)	power gating haarta hai — negative saving	Ex 5
F	Real-world word problem	multi-core GPU, leakage + wake-up combine karo	Ex 6
G	Combined clock+power gating	do techniques stack ki gayi	Ex 7
H	Exam-style twist	DVFS $V_{dd}$ aur $f$ dono ek saath change karta hai	Ex 8

Is page par har numeric answer machine-checked hai Verify block mein.

Ex 1 — Cell A: ordinary clock-gate saving

Worked example Statement

Ek register file normally $α = 0.5$ ke saath toggle karti hai. Clock gating use sirf 20% cycles mein enable karta hai. Us block mein dynamic power kitne percentage se drop hoti hai?

Forecast: Drop guess karo padhne se pehle — kya yeh 20%, 80%, ya kuch aur hai?

Effective activity nikalo. Jab clock sirf 20% cycles run karti hai, block utni hi baar switch karta hai — 20% jitna: $α_{eff} = α \times 0.20 = 0.5 \times 0.20 = 0.1$ Yeh step kyun? Dynamic power $α$ mein linear hai (formula dekho — $α$ aage baitha hai, squared nahi). Clock kitni baar tick karti hai yeh cutting karna $α$ ko usi fraction se cut karta hai.
Powers ka ratio lo. Baaki saare terms ( $C, V_{dd}^{2}, f$ ) gated vs ungated dono mein same hain, isliye cancel ho jaate hain: $\frac{P _{gated}}{P _{ungated}} = \frac{α _{eff}}{α} = \frac{0.1}{0.5} = 0.2$ Yeh step kyun? Hume sirf change ki parwah hai, isliye divide karne se har unchanged factor khatam ho jaata hai — $C$ ya $V_{dd}$ jaanne ki zaroorat nahi.
Saving mein convert karo. $saving = 1 - 0.2 = 0.8 = 80%$ Yeh step kyun? "Saving" woh fraction hai jo humne hatayi, yaani one minus jo bacha.

Verify: $80%$ saving ka matlab hai $20%$ bacha hai; original activity ka $20%$ exactly woh $0.1$ hai jo humne compute kiya. Units: saare dimensionless ratios hain — consistent. ✓

Ex 2 — Cell B: degenerate case (gate karne ko kuch nahi)

Worked example Statement

Ek memory controller har single cycle mein access hota hai (enable hamesha 1 hai). Clock gating yahan kitni dynamic-power saving deta hai?

Forecast: Zero? Negative? Chhota?

Enable fraction set karo. "Har cycle" ka matlab clock 100% time run karti hai: $α_{eff} = α \times 1.0 = α$ Yeh step kyun? Clock gating sirf clock edges rokna kar sakta hai. Agar koi nahi roka, kuch nahi badlega.
Ratio. $\frac{P _{gated}}{P _{ungated}} = \frac{α}{α} = 1 \Rightarrow saving = 1 - 1 = 0%$ Yeh step kyun? Yeh Ex 1 ki degenerate boundary hai: jaise active fraction $\to 100%$ hoti hai, saving $\to 0$ hoti hai.

Verify: Sanity — ek block ko gate karna jo kabhi idle nahi hota, pure overhead hai (tumne ek AND gate add kiya jo bhi switch karta hai). Ideal saving $0%$ hai; real saving thodi negative hai. Humara clean-model answer $0%$ sahi upper edge hai. ✓

Ex 3 — Cell C: clock gating leakage ke liye kuch nahi karta

Worked example Statement

Ek idle ALU clock-gated hai. Uska $I_{leak} = 2 mA$ hai $V_{dd} = 0.9 V$ par. Akele clock gating ke under "sleep" karte waqt kitni static power abhi bhi jalti hai?

Forecast: Kya clock gating isko zero kar deta hai?

Recall karo clock gating kya touch karta hai. Yeh clock ko freeze karta hai, isliye $α \to 0$ aur $P_{dyn} \to 0$ . Lekin $V_{dd}$ abhi bhi connected hai. Yeh step kyun? Leakage path tab exist karta hai jab voltage transistor ke across baith jaati hai — clock iske liye irrelevant hai (dekho Subthreshold Leakage).
Bachne wali static power compute karo. $P_{static} = I_{leak} V_{dd} = 2 \times 1 0^{- 3} A \times 0.9 V = 1.8 \times 1 0^{- 3} W = 1.8 mW$ Yeh step kyun? Yeh exactly woh number hai jo clock gating nahi hata sakta — yahi argument hai Multi-Threshold CMOS aur power gating ke liye.

Verify: Units $A \times V = W$ . ✓ Block abhi bhi $1.8 mW$ leak karta hai; sirf power gating ( $V_{dd}$ cut karna) ise khatam karta hai.

Ex 4 — Cell D: power-gate break-even limit

Yeh page ki sabse important calculation hai: power gating kab worth it hai? Iske liye ek figure hai.

Ex 5 — Cell E: limit se neeche — power gating HAARTA HAI

Worked example Statement

Same block jaise Ex 4 mein ( $t_{BE} = 100 μ s$ ). OS sirf $40 μ s$ ka idle window predict karta hai. Agar hum power-gate karein toh net energy change kya hoga?

Forecast: Bachayenge ya waste karenge? Kitna?

Idle window ke dauran energy saved. $E_{saved} = P_{save} \times t_{idle} = 50 mW \times 40 μ s = 2 μ J$ Yeh step kyun? Saving tabhi accrue hoti hai jab block actually off hota hai.
Fixed wake cost subtract karo. $E_{net} = E_{saved} - E_{wake} = 2 μ J - 5 μ J = - 3 μ J$ Yeh step kyun? Negative result ka matlab hai humne save kiya usse zyada kharch kiya — yahan power gating galti thi.

Verify: $40 μ s < 100 μ s$ , isliye hum Ex 4 ke crossover ke losing side par hain — $E_{net}$ ka sign zaroor negative hona chahiye, aur hai bhi. Sahi action: is chhote idle ke liye clock-gate karo (0-cost, instant wake). ✓

Ex 6 — Cell F: GPU word problem

Worked example Statement

Ek GPU mein 32 shader cores hain; ek game 8 use karta hai, 24 idle chodta hai. Har core $0.9 V$ par $50 mW$ leak karta hai; power-gated switch leakage $\approx 0.4 mW$ per core hai. Idle windows frames ke beech $5 ms$ ki hain, aur har wake mein $8 μ J$ lagte hain. (a) Leakage saved? (b) Kya 5 ms break-even ke baad hai?

Forecast: Roughly kitne watts, aur aaram se break-even ke baad?

Gating se pehle leakage (24 cores). $P_{before} = 24 \times 50 mW = 1200 mW = 1.2 W$ Yeh step kyun? Idle cores independently leak karte hain, isliye total = per-core × count.
Gating ke baad leakage. $P_{after} = 24 \times 0.4 mW = 9.6 mW$ Yeh step kyun? $V_{dd}$ cut karne par sirf tiny switch leakage bachti hai — exactly zero nahi, isliye hum residual term rakhte hain.
Saved power. $P_{save} = 1200 - 9.6 = 1190.4 mW \approx 1.19 W$
Per-core break-even, phir 5 ms se compare karo. $t_{BE} = \frac{E _{wake}}{P _{save,core}} = \frac{8 \times 1 0 ^{- 6} J}{( 50 - 0.4 ) \times 1 0 ^{- 3} W} = 1.613 \times 1 0^{- 4} s \approx 161 μ s$ Yeh step kyun? Break-even per core hota hai (har ek independently jaagta hai). $5 ms = 5000 μ s ≫ 161 μ s$ , isliye gate kar do.

Verify: $1.19 W$ parent note ke GPU figure se match karta hai. $5000/161 \approx 31 \times$ break-even — winning region mein deep hain. ✓ Ek Power Management IC (PMIC) aur driver ise schedule karta hai.

Ex 7 — Cell G: clock + power gating stack karna

Worked example Statement

Ek block $α = 0.4$ , $C = 2 nF$ , $V_{dd} = 1.0 V$ , $f = 1 GHz$ par run karta hai, aur $I_{leak} = 3 mA$ leak karta hai. Teen states mein total power compare karo: (i) active, (ii) clock-gated, (iii) power-gated (assume leakage $\to 0$ ).

Forecast: Kaun si state jeetti hai, aur kya clock gating saari idle power hataata hai?

Active dynamic power. $P_{dyn} = α C V_{dd}^{2} f = 0.4 \times 2 \times 1 0^{- 9} \times 1. 0^{2} \times 1 \times 1 0^{9} = 0.8 W$
Active static power. $P_{static} = I_{leak} V_{dd} = 3 \times 1 0^{- 3} \times 1.0 = 3 \times 1 0^{- 3} W = 3 mW$ Active total $= 0.8 + 0.003 = 0.803 W$ .
Clock-gated: $P_{dyn} \to 0$ , lekin leakage rehti hai. $P_{clk-gated} = 0 + 3 mW = 3 mW$ Yeh step kyun? Cell C ka lesson action mein — clock gating $3 mW$ ko touch nahi kar sakta.
Power-gated: dono terms khatam ho jaate hain. $P_{pwr-gated} \approx 0 W$

Verify: Ordering $0.803 W > 3 mW > 0$ . Clock gating $0.8 W$ dynamic part (bada wala) hataata hai, power gating aakhri $3 mW$ hataata hai. Lambe idle ke liye, power-gate karo; chhote ke liye, clock-gate karo. ✓

Ex 8 — Cell H: exam twist (DVFS V aur f dono ek saath change karta hai)

Worked example Statement

Ek block $V_{dd} = 1.0 V$ , $f = 1 GHz$ par run karta hai. DVFS ise $V_{dd} = 0.8 V$ , $f = 0.7 GHz$ par scale karta hai (same $α, C$ ). Dynamic power kitne fraction se drop hoti hai?

Forecast: Trap yeh hai: kya power $0.8 \times 0.7$ ki tarah scale hoti hai? Dhyan do — voltage squared hai.

Ratio likho, sirf jo badla woh rakho. $\frac{P _{new}}{P _{old}} = \frac{V _{new}^{2} f _{new}}{V _{old}^{2} f _{old}}$ Yeh step kyun? $α$ aur $C$ unchanged hain, isliye cancel ho jaate hain; sirf $V^{2}$ aur $f$ bachte hain.
Plug in karo — aur voltage ko square karo. $= \frac{0. 8 ^{2} \times 0.7}{1. 0 ^{2} \times 1.0} = \frac{0.64 \times 0.7}{1} = 0.448$ Yeh step kyun? Squared voltage hi wajah hai ki DVFS itna powerful hai: sirf 20% voltage cut se $0. 8^{2} = 0.64$ milta hai, yani frequency se pehle hi 36% power drop.
Saving. $1 - 0.448 = 0.552 = 55.2%$

Verify: Naive (un-squared) guess hoga $0.8 \times 0.7 = 0.56 \Rightarrow 44%$ saving — galat. Sahi $55.2%$ bada hai exactly isliye kyunki voltage squared enter karta hai. Yahi exam trap hai. ✓

Recall Quick self-test

$30 μ s$ idle par power gating jab $t_{BE} = 100 μ s$ — achha idea? ::: Nahi — idle break-even se neeche hai; clock gating use karo (Cell E). Clock gating leakage zero kar deta hai? ::: Nahi — leakage ke liye $V_{dd}$ cut chahiye, yaani power gating (Cell C). DVFS $1.0 V$ se $0.8 V$ (same $f$ ) — dynamic power ratio? ::: $0. 8^{2} = 0.64$ .