Power gating and clock gating: Question bank — Hardware deep dive

This is a rapid-fire trap bank for the parent topic. Each line is a Question ::: Answer. Cover the answer, say your reasoning out loud, then reveal. If your gut said "yes/no" without a why, you fell in the trap.

Before we start, two words we lean on constantly:

Recall The two power buckets in one breath

Dynamic power = energy spent switching nodes up and down (only happens when something toggles). Static / leakage power = energy that trickles away just because $V_{dd}$ is connected, even with nothing moving. Clock gating attacks the first; power gating attacks both. See Dynamic and Static Power.

True or false — justify

TF — Clock gating reduces both dynamic and static power.

False. It only freezes the clock so flip-flops stop toggling (kills dynamic power);

V_{dd}

is still connected, so leakage keeps flowing.

TF — A clock-gated block instantly loses its stored data.

False. The opposite — because power stays on, the flip-flops hold their state with zero effort. That's why clock gating has no state-retention cost.

TF — Power gating always saves more total energy than clock gating.

False. It saves more power while asleep, but the wake-up energy (turning the switch on, restoring state) can exceed the savings if the idle window is short.

TF — Adding a clock gate can never increase the number of gates a signal passes through.

False. You insert at least an AND (and often a latch) into the clock path, adding delay and area — a real, if small, overhead.

TF — The activity factor

α

can equal exactly

0

for a well clock-gated block.

True (for that block). With the clock held constant, its flip-flops make no transitions, so their contribution to

α C V_{dd}^{2} f

vanishes.

TF — Power gating drives the leakage of the gated block to exactly zero.

False. It drops to ~99% lower, but the power switch itself leaks a tiny amount, and virtual-rail charge bleeds — call it "near zero," never zero.

TF — A retention flip-flop keeps its whole master-slave pair powered during sleep.

False. Only the small slave (retention) latch stays on an always-on rail; the master and its logic are powered down to actually save leakage.

TF — Clock gating and power gating are mutually exclusive; you pick one per block.

False. They compose: clock-gate for short idle bursts (μs), then power-gate the same block once idle stretches into ms.

TF — Lowering

V_{dd}

via DVFS is a form of clock gating.

False. DVFS scales voltage/frequency to reduce power on active work; clock gating stops the clock on idle work. Different levers, often used together.

Spot the error

"Clock gating cuts

V_{dd}

to the block." — what's wrong?

Clock gating never touches

V_{dd}

; it gates the clock signal. Cutting

V_{dd}

is power gating's job.

"We used a plain AND gate for the enable, so the clock is guaranteed glitch-free." — error?

A bare AND glitches if enable changes while clk = 1, chopping a partial clock edge. You need a latch that samples enable on the negative edge to hold it stable during the high phase.

"Since dynamic power is

α C V_{dd}^{2} f

and we halved

f

, we halved dynamic power for free." — error?

Halving

f

halves throughput too — that's DVFS, not gating, and it slows the work. Gating instead sets

α \to 0

for idle blocks without touching active-block frequency.

"After power gating we just re-assert the clock and the pipeline resumes exactly where it left off." — error?

Power gating erases ordinary flip-flop state. You must restore from retention cells or memory first; a plain block wakes up with garbage.

"Leakage is negligible, so power gating is pointless on modern chips." — error?

In sub-45 nm / 7 nm nodes leakage can be 30–40% of total power; that's exactly where power gating pays off most.

"The latch in a clock-gating cell stores the flip-flop's data." — error?

It stores the enable signal (holding it stable across the high phase), not the datapath value.

Why questions

Why does stopping the clock save power even if the data input never changes?

Because a toggling clock alone charges/discharges internal flip-flop nodes every edge; freezing the clock removes those transitions regardless of data.

Why can't clock gating help with subthreshold leakage?

Leakage flows because

V_{dd}

sits across transistors, independent of switching. Clock gating leaves

V_{dd}

connected, so the leak path is untouched — see Subthreshold Leakage.

Why use a [[Multi-Threshold CMOS|high-

V_{t h}

]] transistor for the power switch specifically?

The switch is off during sleep, so we want its own leakage tiny; a high-threshold device leaks far less, maximizing the savings of the block behind it.

Why do we sample the enable on the negative clock edge in glitch-free clock gating?

So the enable settles while clk = 0 (the AND output is already low), guaranteeing the enable is stable before clk rises — no partial edge can form.

Why does power gating need a wake-up latency budget while clock gating does not?

The power switch must physically re-charge the block's supply rail and state must be restored; clock gating just un-gates a signal, ready next edge.

Why place power switches in per-block/domain granularity rather than one giant switch for the chip?

Fine-grained domains let you sleep only idle blocks while others run, and smaller switches ramp the rail faster with less inrush current handled by the Power Management IC (PMIC).

Why does the OS/driver, not the hardware alone, decide when to power-gate a GPU core?

Only software knows the predicted idle length; power gating pays off only when idle time exceeds the wake-up cost, which is a scheduling decision.

Edge cases

If a block is idle for just 5 ns but wake-up takes 200 ns, which technique?

Clock gating — it's instant to enter and exit. Power gating's 200 ns overhead would dwarf a 5 ns idle window.

What happens to a clock-gated block's leakage during a long idle?

It keeps leaking the whole time, so a long idle eventually favors switching to power gating despite its wake-up cost.

What's the risk if enable glitches for one cycle during clock gating?

A spurious clock edge can latch wrong data or double-clock a flip-flop — a functional bug, not just wasted power. Hence the mandatory enable latch.

Zero-latency requirement (e.g. real-time interrupt handler): gate it?

Clock-gate at most; never power-gate the handler's block, because the wake-up latency could miss the deadline.

A block is fully active every cycle (100% utilization): does gating help?

No — there's no idle time for either technique to exploit. Use DVFS or architectural changes instead.

Power-gated block with no retention cells and no memory save: what state survives?

None of the ordinary registers survive; the block resets to unknown/initial state on wake, so it's only safe where losing state is acceptable.