Power gating and clock gating: Question bank — Hinglish deep dive

6.4.4 · D5 · Hardware › Power, Thermal & Reliability › Power gating and clock gating

Yeh parent topic ke liye ek rapid-fire trap bank hai. Har line ek Question ::: Answer hai. Answer ko cover karo, apni reasoning zabar se bolo, phir reveal karo. Agar tumhara gut "yes/no" bola bina why ke, tum trap mein phans gaye.

Shuru karne se pehle, do words jo hum baar baar use karte hain:

Recall Do power buckets ek hi saanс mein

Dynamic power = energy jo nodes ko upar-neeche switch karne mein kharch hoti hai (sirf tab hoti hai jab kuch toggle kare). Static / leakage power = energy jo sirf isliye trickle hoti rehti hai kyunki $V_{dd}$ connected hai, chahe kuch move na ho. Clock gating pehle waale ko attack karta hai; power gating dono ko. Dekho Dynamic and Static Power.

True or false — justify karo

TF — Clock gating dynamic aur static dono power reduce karta hai.

False. Yeh sirf clock ko freeze karta hai taaki flip-flops toggle karna band kar dein (dynamic power khatam);

V_{dd}

abhi bhi connected hai, isliye leakage behti rehti hai.

TF — Clock-gated block instantly apna stored data kho deta hai.

False. Bilkul ulta — kyunki power on rehti hai, flip-flops apni state bina kisi effort ke hold karte hain. Isliye clock gating ka koi state-retention cost nahi hota.

TF — Power gating hamesha clock gating se zyada total energy bachata hai.

False. Yeh sote waqt zyada power bachata hai, lekin wake-up energy (switch on karna, state restore karna) savings se zyada ho sakti hai agar idle window chhota ho.

TF — Clock gate add karna kabhi bhi ek signal ke raaste mein gates ki sankhya nahi badha sakta.

False. Tum clock path mein kam se kam ek AND (aur aksar ek latch) insert karte ho, jo delay aur area add karta hai — ek real, agar chhota, overhead hai.

TF — Activity factor

α

ek achhi tarah se clock-gated block ke liye bilkul

0

ho sakta hai.

True (us block ke liye). Clock constant hold rehne par, uske flip-flops koi transitions nahi karte, toh

α C V_{dd}^{2} f

mein unka contribution zero ho jaata hai.

TF — Power gating gated block ki leakage ko exactly zero tak le jaata hai.

False. Yeh ~99% tak girta hai, lekin power switch khud thodi si leakage karta hai, aur virtual-rail charge bleed hoti hai — isse "near zero" kaho, kabhi zero nahi.

TF — Ek retention flip-flop sleep ke dauran apna poora master-slave pair powered rakhta hai.

False. Sirf chhota slave (retention) latch always-on rail par on rehta hai; master aur uski logic leakage bachane ke liye power down ho jaati hai.

TF — Clock gating aur power gating mutually exclusive hain; tum ek block ke liye ek choose karte ho.

False. Yeh compose karte hain: chhote idle bursts (μs) ke liye clock-gate karo, phir jab idle ms tak stretch ho jaye toh usi block ko power-gate karo.

TF — DVFS ke zariye

V_{dd}

lower karna clock gating ka ek form hai.

False. DVFS active kaam par power reduce karne ke liye voltage/frequency scale karta hai; clock gating idle kaam par clock band karta hai. Alag levers hain, aksar saath use hote hain.

Error dhundho

"Clock gating block ko

V_{dd}

cut karta hai." — kya galat hai?

Clock gating kabhi

V_{dd}

ko nahi chhuta; yeh clock signal ko gate karta hai.

V_{dd}

cut karna power gating ka kaam hai.

"Humne enable ke liye plain AND gate use kiya, toh clock guaranteed glitch-free hai." — error?

Ek bare AND glitch karta hai agar enable tab change ho jab clk = 1 ho, ek partial clock edge chop ho jaati hai. Tumhe ek latch chahiye jo negative edge par enable sample kare taaki high phase ke dauran stable rahe.

"Kyunki dynamic power

α C V_{dd}^{2} f

hai aur humne

f

half kar diya, humne dynamic power free mein half kar di." — error?

f

half karna throughput bhi half kar deta hai — yeh DVFS hai, gating nahi, aur yeh kaam slow karta hai. Gating iske bajaye idle blocks ke liye

α \to 0

set karta hai bina active-block frequency ko touch kiye.

"Power gating ke baad hum bas clock re-assert karte hain aur pipeline exactly wahin se resume karti hai jahan chhodi thi." — error?

Power gating ordinary flip-flop state erase kar deta hai. Tumhe pehle retention cells ya memory se restore karna hoga; ek plain block garbage ke saath wake up hoga.

"Leakage negligible hai, isliye modern chips par power gating pointless hai." — error?

Sub-45 nm / 7 nm nodes mein leakage total power ka 30–40% ho sakta hai; exactly wahin power gating sabse zyada faayda karta hai.

"Clock-gating cell mein latch flip-flop ka data store karta hai." — error?

Yeh enable signal store karta hai (high phase ke dauran stable rakhne ke liye), datapath value nahi.

Why questions

Clock rokne se power kyun bachti hai chahe data input kabhi change na ho?

Kyunki toggling clock akele internal flip-flop nodes ko har edge par charge/discharge karta hai; clock freeze karne se data ki parwah kiye bina woh transitions hat jaate hain.

Clock gating subthreshold leakage mein kyun help nahi kar sakta?

Leakage isliye flow karti hai kyunki

V_{dd}

transistors ke across baith jaati hai, switching se independent. Clock gating

V_{dd}

connected chhod deta hai, toh leak path untouched rehta hai — dekho Subthreshold Leakage.

Power switch ke liye specifically [[Multi-Threshold CMOS|high-

V_{t h}

]] transistor kyun use karte hain?

Switch sleep ke dauran off rehta hai, toh hum chahte hain uski khud ki leakage tiny ho; ek high-threshold device bahut kam leakage karta hai, uske peeche block ki savings maximize karta hai.

Glitch-free clock gating mein hum negative clock edge par enable sample kyun karte hain?

Taaki enable clk = 0 ke dauran settle ho jaye (AND output already low hai), guarantee karta hai ki enable clk rise hone se pehle stable hai — koi partial edge form nahi ho sakta.

Power gating ko wake-up latency budget ki zarurat kyun hai jabki clock gating ko nahi?

Power switch ko physically block ki supply rail re-charge karni hogi aur state restore karni hogi; clock gating bas ek signal un-gate karta hai, agले edge par ready.

Power switches ko ek chip ke liye ek giant switch ki jagah per-block/domain granularity mein kyun rakhte hain?

Fine-grained domains sirf idle blocks ko soone dete hain jabki doosre run karte hain, aur chhote switches rail ko tezi se ramp karte hain kam inrush current ke saath jo Power Management IC (PMIC) handle karta hai.

OS/driver, hardware akela nahi, kyun decide karta hai ki GPU core ko power-gate kab karna hai?

Sirf software ko predicted idle length pata hoti hai; power gating tab hi faayda karta hai jab idle time wake-up cost se zyada ho, jo ek scheduling decision hai.

Edge cases

Agar ek block sirf 5 ns ke liye idle hai lekin wake-up mein 200 ns lagte hain, toh kaun sa technique?

Clock gating — enter aur exit karna instant hai. Power gating ka 200 ns overhead ek 5 ns idle window se kahin zyada hoga.

Clock-gated block ki leakage lambe idle ke dauran kya hoti hai?

Yeh poore samay leakti rehti hai, isliye ek lamba idle eventually power gating ki taraf shift ho jaata hai uski wake-up cost ke bawajood.

Agar clock gating ke dauran enable ek cycle ke liye glitch kare toh kya hoga?

Ek spurious clock edge galat data latch kar sakta hai ya flip-flop ko double-clock kar sakta hai — yeh ek functional bug hai, sirf waste hone wali power nahi. Isliye mandatory enable latch hai.

Zero-latency requirement (jaise real-time interrupt handler): gate karo?

Zyada se zyada clock-gate karo; handler ke block ko kabhi power-gate mat karo, kyunki wake-up latency deadline miss kar sakti hai.

Ek block har cycle fully active hai (100% utilization): kya gating help karta hai?

Nahi — kisi bhi technique ke liye exploit karne ke liye koi idle time nahi hai. DVFS ya architectural changes use karo.

Power-gated block bina retention cells aur bina memory save ke: kaun si state bachti hai?

Koi bhi ordinary registers survive nahi karte; block wake par unknown/initial state mein reset ho jaata hai, toh yeh sirf wahin safe hai jahan state khoना acceptable ho.