Exercises — Power gating and clock gating

Clock gating freezes the clock so flip-flops stop toggling, so $\alpha \to 0$ for that block. But $V_{\text{dd}}$ is still connected, so leakage keeps flowing.

• Clock gating → removes dynamic power only.

Power gating physically disconnects $V_{\text{dd}}$ through a header/footer switch. No supply → no toggling and no leakage path.

• Power gating → removes both dynamic and static power.

Clock gating drives $==\alpha ==$ (the activity factor) toward $0$. A held-low clock means the flip-flop's internal nodes never charge or discharge — zero transitions is exactly $\alpha =0$. Because $\alpha$ multiplies every other factor, $\alpha =0\Rightarrow P_{\text{dyn}}=0$ for that block, regardless of how big $C$, $V_{\text{dd}}$, or $f$ are.

Step 1 — effective activity. When the block is gated off it contributes $\alpha =0$; when active it contributes $0.5$. Averaged over time: ${\alpha }_{\text{eff}}=0.5\times 0.25=0.125$ Step 2 — saving. Since only $\alpha$ changed, the power ratio is the $\alpha$ ratio: $\text{saving}=\frac{0.5-0.125}{0.5}=\frac{0.375}{0.5}=0.75=75\%.$ Clock gating saves 75 % of the register file's dynamic power. Note it equals $1-(\text{duty cycle})=1-0.25$ — a handy shortcut.

Before: all $24$ idle cores leak fully: $P_{\text{before}}=24\times 50\text{mW}=1200\text{mW}=1.2\text{W}.$ After: the $24$ gated cores leak the residual switch leakage: $P_{\text{after}}=24\times 0.4\text{mW}=9.6\text{mW}=0.0096\text{W}.$ Saving: $1.2-0.0096=1.1904\text{W}\approx 1.19\text{W}.$ That is a $\frac{1.1904}{1.2}=99.2\%$ leakage reduction on the idle cores.

Model. Staying powered for time $t$ wastes $E_{\text{stay}}=P_{\text{leak}}t$. Power gating instead pays $E_{\text{wake}}$ once (and ~zero during sleep). Break-even is where the two are equal: $P_{\text{leak}}{t}_{\text{be}}=E_{\text{wake}}.$ Solve. $t_{\text{be}}=\frac{E_{\text{wake}}}{P_{\text{leak}}}=\frac{12\times 10^{-6}\text{J}}{80\times 10^{-3}\text{W}}=1.5\times 10^{-4}\text{s}=150\mu \text{s}.$ Interpretation. Idle longer than $150\mu \text{s}$ → power gating wins. Shorter → the wake-up energy exceeds the leakage you'd have saved, so you should clock-gate (zero wake-up cost) instead. See the break-even figure below.

Energy-wise, $500\mu \text{s}\gg t_{\text{be}}$, so power gating would save energy. But latency is a hard constraint. Wake-up takes $200\text{ns}$ and the deadline is only $150\text{ns}$: $200\text{ns}>150\text{ns}\Rightarrow \text{deadline missed.}$ So the unit cannot be power-gated here. Fallback: clock gate it (wake-up = $0$ cycles), accepting the leakage. This is exactly the two-axis trade-off — energy alone says "yes," latency says "no," and latency wins.

Per-period energy, clock-gating only.

• Active phase ($100\mu \text{s}$): dynamic + leakage $=(200+80)\text{mW}$. $E_{\text{act}}=0.28\text{W}\times 100\times 10^{-6}\text{s}=28\mu \text{J}.$
• Idle phase ($900\mu \text{s}$): clock-gated, so dynamic $=0$, leakage stays $80\text{mW}$: $E_{\text{idle,cg}}=0.08\text{W}\times 900\times 10^{-6}\text{s}=72\mu \text{J}.$
• Total per period $=28+72=100\mu \text{J}$ over $1\text{ms}$: $P_{\text{cg}}=\frac{100\mu \text{J}}{1\text{ms}}=100\text{mW}.$

Now add power gating for the idle window. Idle $=900\mu \text{s}>t_{\text{be}}=150\mu \text{s}$, so gating wins. Idle leakage energy $\to 0$; pay $E_{\text{wake}}=12\mu \text{J}$ once: $E_{\text{idle,pg}}=0+12\mu \text{J}=12\mu \text{J}.$

• New total $=28+12=40\mu \text{J}$ per $1\text{ms}$: $P_{\text{combined}}=\frac{40\mu \text{J}}{1\text{ms}}=40\text{mW}.$ Result: clock-gate only $\to 100\text{mW}$; clock + power gate $\to 40\text{mW}$, a further $60\%$ cut on top of clock gating. A real Power Management IC (PMIC) orchestrates exactly this hand-off.

Dynamic power $\propto V_{\text{dd}}^{2}f$. If frequency scales linearly with voltage (a common first-order model, $f\propto V_{\text{dd}}$), then $P_{\text{dyn}}\propto V_{\text{dd}}^3$: $P_{\text{new}}=200\text{mW}\times {\left(\frac{0.8}{1.0}\right)}^3=200\times 0.512=102.4\text{mW}.$ Comment: DVFS nearly halves active dynamic power but the block is still running and still leaking. DVFS optimises the active phase; gating optimises the idle phase. They are complementary, not substitutes — a good design does DVFS while working and gates when idle.

Step 1 — timings. Period $2\text{ms}$, active $5\%=100\mu \text{s}$, idle $=1900\mu \text{s}$.

Step 2 — is power gating legal? Break-even idle: $t_{\text{be}}=\frac{15\mu \text{J}}{60\text{mW}}=250\mu \text{s}.$ Idle $1900\mu \text{s}>250\mu \text{s}$ ✓ (energy says gate). Latency $300\text{ns}\le 2\mu \text{s}$ deadline ✓ (timing says gate). Both gates pass → power-gate the idle window, and clock-gate is redundant there since power is fully removed.

Step 3 — energy per period.

• Active: $E_{\text{act}}=(300+60)\text{mW}\times 100\mu \text{s}=0.36\text{W}\times 100\times 10^{-6}\text{s}=36\mu \text{J}.$
• Idle (power-gated): leakage $\to 0$, pay wake-up once: $E_{\text{idle}}=15\mu \text{J}.$
• Total $=36+15=51\mu \text{J}$ per $2\text{ms}$.

Step 4 — average power. $P_{\text{avg}}=\frac{51\mu \text{J}}{2\text{ms}}=25.5\text{mW}.$ Compare to "always powered, clock-gate idle": active $36\mu \text{J}$ + idle leakage $60\text{mW}\times 1900\mu \text{s}=114\mu \text{J}$, total $150\mu \text{J}\Rightarrow 75\text{mW}$. Power gating cuts this to $25.5\text{mW}$ — a $66\%$ reduction. Save critical state with Retention Flip-Flops before shutdown; a Hierarchical Clock Distribution tree hosts the clock gates for the active phase.

Any two of:

1. Latency / deadline — wake-up may exceed the required response time (as in L3.2), even when energy math favours gating.
2. State loss cost — without Retention Flip-Flops the block must save/restore large state (register maps, caches), and the restore energy/time can exceed the leakage saved.
3. Inrush / rail noise — turning a large header switch on injects a current surge that can droop $V_{\text{dd}}$ for neighbours; the Power Management IC (PMIC) must stagger wake-ups, adding latency.
4. Area / verification overhead — power switches, isolation cells, and an extra power domain cost silicon area and design/verification effort not justified for a block that's rarely idle long enough.

Break-even idle time formula ::: $t_{\text{be}}=E_{\text{wake}}/P_{\text{leak}}$ Effective activity factor under clock gating ::: ${\alpha }_{\text{eff}}={\alpha }_{\text{active}}\times \text{duty cycle}$ Dynamic power scaling with voltage (with $f\propto V$) ::: $P_{\text{dyn}}\propto V_{\text{dd}}^3$ Which axis can veto a power-gating decision even when energy favours it ::: wake-up latency vs. deadline