Exercises — Power gating and clock gating

Clock gating clock ko freeze kar deta hai jisse flip-flops toggle karna band kar dete hain, toh us block ke liye $\alpha \to 0$ ho jaata hai. Lekin $V_{\text{dd}}$ abhi bhi connected hai, isliye leakage flow karta rehta hai.

• Clock gating → sirf dynamic power remove karta hai.

Power gating $V_{\text{dd}}$ ko physically ek header/footer switch ke zariye disconnect kar deta hai. Supply nahi → na toggling aur na leakage path.

• Power gating → dono dynamic aur static power remove karta hai.

Clock gating $==\alpha ==$ (activity factor) ko $0$ ki taraf drive karta hai. Ek held-low clock ka matlab hai flip-flop ke internal nodes kabhi charge ya discharge nahi hote — zero transitions exactly $\alpha =0$ hai. Kyunki $\alpha$ baaki sabhi factors ko multiply karta hai, $\alpha =0\Rightarrow P_{\text{dyn}}=0$ us block ke liye, chahe $C$, $V_{\text{dd}}$, ya $f$ kitne bhi bade kyun na hon.

Step 1 — effective activity. Jab block gated off hota hai toh $\alpha =0$ contribute karta hai; jab active hota hai toh $0.5$ contribute karta hai. Time par average karke: ${\alpha }_{\text{eff}}=0.5\times 0.25=0.125$ Step 2 — saving. Kyunki sirf $\alpha$ badla, power ratio $\alpha$ ratio hai: $\text{saving}=\frac{0.5-0.125}{0.5}=\frac{0.375}{0.5}=0.75=75\%.$ Clock gating register file ki dynamic power ka 75% save karta hai. Note karein yeh $1-(\text{duty cycle})=1-0.25$ ke barabar hai — ek handy shortcut.

Pehle: saare $24$ idle cores poori tarah leak karte hain: $P_{\text{before}}=24\times 50\text{mW}=1200\text{mW}=1.2\text{W}.$ Baad mein: $24$ gated cores residual switch leakage se leak karte hain: $P_{\text{after}}=24\times 0.4\text{mW}=9.6\text{mW}=0.0096\text{W}.$ Saving: $1.2-0.0096=1.1904\text{W}\approx 1.19\text{W}.$ Yeh idle cores par $\frac{1.1904}{1.2}=99.2\%$ leakage reduction hai.

Model. $t$ time tak powered rehne mein $E_{\text{stay}}=P_{\text{leak}}t$ waste hoti hai. Power gating iske bajaye ek baar $E_{\text{wake}}$ pay karta hai (aur sleep ke dauran ~zero). Break-even wahan hai jahan dono equal hain: $P_{\text{leak}}{t}_{\text{be}}=E_{\text{wake}}.$ Solve. $t_{\text{be}}=\frac{E_{\text{wake}}}{P_{\text{leak}}}=\frac{12\times 10^{-6}\text{J}}{80\times 10^{-3}\text{W}}=1.5\times 10^{-4}\text{s}=150\mu \text{s}.$ Interpretation. $150\mu \text{s}$ se zyada idle → power gating jeet ta hai. Kam → wake-up energy us leakage se zyada ho jaati hai jo aap save karte, isliye clock-gate (zero wake-up cost) karna chahiye. Neeche break-even figure dekhein.

Energy ke hisaab se, $500\mu \text{s}\gg t_{\text{be}}$, toh power gating energy save karega. Lekin latency ek hard constraint hai. Wake-up mein $200\text{ns}$ lagte hain aur deadline sirf $150\text{ns}$ hai: $200\text{ns}>150\text{ns}\Rightarrow \text{deadline missed.}$ Toh unit ko yahan power-gate nahi kiya ja sakta. Fallback: ise clock gate karein (wake-up = $0$ cycles), leakage accept karte hue. Yeh exactly woh two-axis trade-off hai — energy akela kehta hai "haan," latency kehti hai "nahi," aur latency jeet ti hai.

Per-period energy, sirf clock-gating.

• Active phase ($100\mu \text{s}$): dynamic + leakage $=(200+80)\text{mW}$. $E_{\text{act}}=0.28\text{W}\times 100\times 10^{-6}\text{s}=28\mu \text{J}.$
• Idle phase ($900\mu \text{s}$): clock-gated, toh dynamic $=0$, leakage $80\text{mW}$ rehti hai: $E_{\text{idle,cg}}=0.08\text{W}\times 900\times 10^{-6}\text{s}=72\mu \text{J}.$
• Total per period $=28+72=100\mu \text{J}$ over $1\text{ms}$: $P_{\text{cg}}=\frac{100\mu \text{J}}{1\text{ms}}=100\text{mW}.$

Ab idle window ke liye power gating add karein. Idle $=900\mu \text{s}>t_{\text{be}}=150\mu \text{s}$, toh gating jeet ta hai. Idle leakage energy $\to 0$; ek baar $E_{\text{wake}}=12\mu \text{J}$ pay karein: $E_{\text{idle,pg}}=0+12\mu \text{J}=12\mu \text{J}.$

• Naya total $=28+12=40\mu \text{J}$ per $1\text{ms}$: $P_{\text{combined}}=\frac{40\mu \text{J}}{1\text{ms}}=40\text{mW}.$ Result: sirf clock-gate $\to 100\text{mW}$; clock + power gate $\to 40\text{mW}$, clock gating ke upar se aur $60\%$ cut. Ek real Power Management IC (PMIC) exactly yahi hand-off orchestrate karta hai.

Dynamic power $\propto V_{\text{dd}}^{2}f$. Agar frequency voltage ke saath linearly scale hoti hai (ek common first-order model, $f\propto V_{\text{dd}}$), toh $P_{\text{dyn}}\propto V_{\text{dd}}^3$: $P_{\text{new}}=200\text{mW}\times {\left(\frac{0.8}{1.0}\right)}^3=200\times 0.512=102.4\text{mW}.$ Comment: DVFS active dynamic power ko lagbhag aadha kar deta hai lekin block abhi bhi chal raha hai aur abhi bhi leak kar raha hai. DVFS active phase optimize karta hai; gating idle phase optimize karta hai. Yeh complementary hain, substitutes nahi — ek accha design kaam karte waqt DVFS karta hai aur idle hone par gate karta hai.

Step 1 — timings. Period $2\text{ms}$, active $5\%=100\mu \text{s}$, idle $=1900\mu \text{s}$.

Step 2 — kya power gating legal hai? Break-even idle: $t_{\text{be}}=\frac{15\mu \text{J}}{60\text{mW}}=250\mu \text{s}.$ Idle $1900\mu \text{s}>250\mu \text{s}$ ✓ (energy kehti hai gate karo). Latency $300\text{ns}\le 2\mu \text{s}$ deadline ✓ (timing kehti hai gate karo). Dono gates pass → idle window ko power-gate karein, aur clock-gate wahan redundant hai kyunki power poori tarah remove ho gayi hai.

Step 3 — energy per period.

• Active: $E_{\text{act}}=(300+60)\text{mW}\times 100\mu \text{s}=0.36\text{W}\times 100\times 10^{-6}\text{s}=36\mu \text{J}.$
• Idle (power-gated): leakage $\to 0$, ek baar wake-up pay karein: $E_{\text{idle}}=15\mu \text{J}.$
• Total $=36+15=51\mu \text{J}$ per $2\text{ms}$.

Step 4 — average power. $P_{\text{avg}}=\frac{51\mu \text{J}}{2\text{ms}}=25.5\text{mW}.$ Compare karein "hamesha powered, clock-gate idle" se: active $36\mu \text{J}$ + idle leakage $60\text{mW}\times 1900\mu \text{s}=114\mu \text{J}$, total $150\mu \text{J}\Rightarrow 75\text{mW}$. Power gating ise $25.5\text{mW}$ tak le aata hai — ek $66\%$ reduction. Shutdown se pehle critical state Retention Flip-Flops ke saath save karein; ek Hierarchical Clock Distribution tree active phase ke liye clock gates host karta hai.

Inme se koi bhi do:

1. Latency / deadline — wake-up required response time se zyada ho sakta hai (jaise L3.2 mein), tab bhi jab energy math gating favour karta ho.
2. State loss cost — Retention Flip-Flops ke bina block ko bada state (register maps, caches) save/restore karna padta hai, aur restore energy/time saved leakage se zyada ho sakti hai.
3. Inrush / rail noise — ek bada header switch on karna ek current surge inject karta hai jo neighbours ke liye $V_{\text{dd}}$ droop kar sakta hai; Power Management IC (PMIC) ko wake-ups stagger karne padte hain, latency badhti hai.
4. Area / verification overhead — power switches, isolation cells, aur ek extra power domain silicon area aur design/verification effort cost karte hain jo ek block ke liye justify nahi hote jo rarely itne lambe time ke liye idle rehta ho.

Break-even idle time formula ::: $t_{\text{be}}=E_{\text{wake}}/P_{\text{leak}}$ Clock gating ke under effective activity factor ::: ${\alpha }_{\text{eff}}={\alpha }_{\text{active}}\times \text{duty cycle}$ Voltage ke saath dynamic power scaling (jab $f\propto V$) ::: $P_{\text{dyn}}\propto V_{\text{dd}}^3$ Kaun sa axis power-gating decision ko veto kar sakta hai tab bhi jab energy favour kare ::: wake-up latency vs. deadline