Foundations — Power gating and clock gating

Before you can understand power and clock gating, you must be able to read every symbol the parent note throws at you. This page builds each one from nothing — plain words first, then a picture, then why the topic needs it. Read top to bottom; each idea rests on the one above it.

1. Voltage, current, and power — the three words everything else is built on

Look at the picture: a tank (voltage/pressure) drives water (current) through a pipe. Widen the flow or raise the pressure and the wheel spins faster — that spinning is power. This single idea, $P=V\times I$, is the ancestor of every power formula in the parent note.

Why the topic needs it: every technique on the parent page is judged by one number — how many watts it saves. If you can't read $P=VI$, you can't read the savings.

2. The transistor — the tiny switch, and where "leakage" hides

PMOS and NMOS — two flavours

You need these two names because the parent note's header switch is a PMOS (sits between $V_{\text{dd}}$ and the block) and the footer switch is an NMOS (sits between the block and ground). See Multi-Threshold CMOS for why the fat, low-leakage variety is chosen for those switches.

3. Capacitance $C$ — why switching costs energy

Look at the two buckets in the figure. Charging the bucket to voltage $V_{\text{dd}}$ stores energy proportional to $C{V}_{\text{dd}}^2$. Every time a signal toggles, one bucket-fill of energy is spent. This is exactly why toggling burns power — and why stopping the toggles (clock gating) saves it.

4. Frequency $f$ and the clock

Each clock beat is when flip-flops sample new data — and each beat can trigger toggles that fill buckets. So more beats per second = more bucket-fills per second = more power. That is why $f$ appears in the dynamic-power formula, and why the Hierarchical Clock Distribution tree that carries this clock everywhere is itself a power hog worth gating.

5. The activity factor $\alpha$ — the "how busy" knob

Why the topic needs it: clock gating works by forcing $\alpha \to 0$ for an idle block. Freeze the clock and no bucket gets filled, so the block's $\alpha$ collapses to zero even though the frequency $f$ of the global clock is unchanged. $\alpha$ is the exact dial that gating turns.

6. Putting them together — the dynamic power formula

Each factor is now a symbol you defined:

• $\alpha$ — fraction toggling (§5),
• $C$ — the buckets (§3),
• $V_{\text{dd}}^2$ — the push, squared because filling to voltage $V$ costs $\propto V^2$ (§3),
• $f$ — beats per second (§4).

See Dynamic and Static Power for the full breakdown. This is the formula clock gating minimises (by killing $\alpha$).

7. Leakage — the current that flows when nothing happens

The figure contrasts the two power types on a timeline. Dynamic power spikes only on toggles (the tall bars). Static/leakage power is the flat baseline that never goes away as long as $V_{\text{dd}}$ is connected — even between toggles, even with the clock frozen.

8. Logic gates and the enable signal

9. The prerequisite map

Every arrow is a dependency: you cannot understand the box it points to until you own the box it points from.

Equipment checklist

Self-test — cover the right side and answer before revealing.