Foundations — Power gating and clock gating

6.4.4 · D1 · Hardware › Power, Thermal & Reliability › Power gating and clock gating

Isse pehle ki aap power aur clock gating samjhein, aapko parent note ke har symbol ko padhna aana chahiye. Yeh page har ek ko zero se build karta hai — pehle plain words mein, phir ek picture, phir kyun topic ko uski zaroorat hai. Upar se neeche padho; har idea uske upar wale idea par tikaa hua hai.

1. Voltage, current, aur power — teen words jis par baaki sab bana hai

Picture dekho: ek tank (voltage/pressure) paani (current) ko pipe ke through drive karta hai. Flow ko badhaao ya pressure badhao aur chakka tezi se ghoomega — woh ghumna power hai. Yeh ek idea, $P=V\times I$, parent note ke har power formula ka ancestor hai.

Topic ko iska kyun zaroorat hai: parent page par har technique ko ek number se judge kiya jaata hai — kitne watts bachaye. Agar aap $P=VI$ nahi padh sakte, toh aap savings nahi padh sakte.

2. Transistor — woh tiny switch, aur "leakage" kahan chhupta hai

PMOS aur NMOS — do flavours

Aapko yeh do names isliye chahiye kyunki parent note ka header switch ek PMOS hai ($V_{\text{dd}}$ aur block ke beech baithta hai) aur footer switch ek NMOS hai (block aur ground ke beech baithta hai). Multi-Threshold CMOS dekho yeh samjhne ke liye ki un switches ke liye mota, kam-leakage wala variety kyun choose kiya jaata hai.

3. Capacitance $C$ — kyun switching mein energy lagti hai

Figure mein do buckets dekho. Bucket ko voltage $V_{\text{dd}}$ tak charge karna $C{V}_{\text{dd}}^2$ ke proportional energy store karta hai. Jab bhi koi signal toggle karta hai, ek bucket-fill ki energy kharch hoti hai. Yahi wajah hai ki toggling power burn karta hai — aur isliye toggles rokna (clock gating) use bachata hai.

4. Frequency $f$ aur clock

Har clock beat woh hota hai jab flip-flops naya data sample karte hain — aur har beat un toggles ko trigger kar sakta hai jo buckets bharte hain. Toh zyada beats per second = zyada bucket-fills per second = zyada power. Isliye $f$ dynamic-power formula mein aata hai, aur isliye Hierarchical Clock Distribution tree jo is clock ko har jagah le jaata hai woh khud ek power hog hai jise gate karna worth hai.

5. Activity factor $\alpha$ — "kitna busy" wala knob

Topic ko iska kyun zaroorat hai: clock gating kaam karta hai idle block ke liye $\alpha \to 0$ force karke. Clock freeze karo aur koi bucket nahi bharega, toh block ka $\alpha$ zero par collapse ho jaata hai chahe global clock ki frequency $f$ unchanged ho. $\alpha$ wahi exact dial hai jise gating ghumaata hai.

6. Inhe saath jodna — dynamic power formula

Har factor ab woh symbol hai jo aapne define kiya:

• $\alpha$ — toggling ka fraction (§5),
• $C$ — buckets (§3),
• $V_{\text{dd}}^2$ — push, squared kyunki voltage $V$ tak bharna $\propto V^2$ cost karta hai (§3),
• $f$ — beats per second (§4).

Dynamic and Static Power dekho poore breakdown ke liye. Yahi woh formula hai jo clock gating minimise karta hai ($\alpha$ ko maar ke).

7. Leakage — woh current jo tab bhi flow karta hai jab kuch nahi hota

Figure do power types ko ek timeline par contrast karta hai. Dynamic power sirf toggles par spike karta hai (tall bars). Static/leakage power woh flat baseline hai jo kabhi nahi jaati jab tak $V_{\text{dd}}$ connected hai — toggles ke beech bhi, clock freeze hone par bhi.

8. Logic gates aur enable signal

9. Prerequisite map

Har arrow ek dependency hai: us box ko aap tab tak nahi samajh sakte jab tak aapke paas us box ki ownership na ho jis se arrow aata hai.

Equipment checklist

Self-test — right side cover karo aur reveal karne se pehle jawab do.