Visual walkthrough — Power gating and clock gating

6.4.4 · D2 · Hardware › Power, Thermal & Reliability › Power gating and clock gating

Yeh page parent topic ka central result bilkul scratch se build karta hai: chip ki power actually kahaan jaati hai, aur exactly kaise gating usse kam karti hai. Har step ke liye hum tasveerein use karenge. Koi bhi symbol draw karne se pehle appear nahi hoga.

Chaliye ek single number par agree karke shuru karte hain jise hum chhota banana chahte hain: ek logic block kitni power jalata hai.

---

Step 1 — "Power" ka matlab yahan kya hai

KYA HAI. Ek chip block tiny switches (transistors) ka ek thaila hai jise ek voltage rail se feed kiya jaata hai. "Power" sirf itna hai ki yeh kitni tezi se energy drain karta hai, measured in watts (joules per second). Hum ise do dheron mein baantte hain:

Unhe alag kyun karte hain? Kyunki do gating techniques alag-alag dher par attack karti hain. Agar aapko nahi pata kaun sa dher bada hai, to aap sahi tool nahi chun sakte. (Dherom ke baare mein aur jaankari Dynamic and Static Power mein.)

TASVEER. Do stacked bars: upar "moving charge" ka dher, neeche "quiet leak" ka dher. Is page par sab kuch ek ya dono bars ko chota karne ke baare mein hai.

---

Step 2 — Charge move karne mein energy kyun lagti hai (capacitor)

KYA HAI. Har wire aur gate input capacitor ki tarah behave karta hai: ek bucket jo "1" read karne ke liye charge se bhara jaana chahiye aur "0" read karne ke liye khaali kiya jaana chahiye. Us bucket ki size ko $C$ (uski capacitance) aur rail voltage ko $V_{\text{dd}}$ kehte hain.

Capacitor kyun, kuch aur kyun nahi? Kyunki charge teleport nahi hota. Ek wire ko $V_{\text{dd}}$ tak raise karne ke liye aapko $Q=C{V}_{\text{dd}}$ charge push karna padta hai, aur voltage ke across charge push karne mein energy lagti hai. Yahi physical reason hai ki ek bit flip karna kabhi bhi free nahi hota.

TASVEER. $V_{\text{dd}}$ height par ek tap ke neeche $C$ label kiya hua ek bucket: use bharna (orange) phir dump karna (blue). Ek fill+dump = ek $E_{\text{cycle}}$.

---

Step 3 — Ek flip se flips ki stream tak: dynamic power

KYA HAI. Real circuits ek second mein kai baar flip karte hain. Clock $f$ baar ek second mein tick karti hai (iska frequency), aur sirf ek fraction $\alpha$ buckets actually kisi bhi tick par flip karte hain.

$\alpha$ aur $f$ kyun introduce karein? Power energy per second hai. Isliye hum ek flip ki energy ko multiply karte hain ki kitne flips per second hote hain. $f$ ticks count karta hai; $\alpha$ (activity factor) is baat ka account karta hai ki har bucket har tick par flip nahi karta.

Baad ke liye key observation: agar hum $\alpha \to 0$ force kar sakein, to $P_{\text{dyn}}\to 0$ chahe $C$, $V_{\text{dd}}$, ya $f$ kitne bhi bade kyun na hon. Yahi clock gating ka beej hai.

TASVEER. Ek ticking clock ke neeche buckets ki ek row; sirf fraction $\alpha$ har tick par light up (flip) karte hain. Kam lit buckets = choti bar.

---

Step 4 — Clock gating: $\alpha$ ko zero par ghonta

KYA HAI. Ek flip-flop apne internal nodes tabhi flip karta hai jab uska clock input toggle karta hai. To clock wire par ek gate lagao: real clock aur ek enable line ka AND.

$\text{gated\_clk}=\text{clk}\wedge \text{enable}$

• $\wedge$ — logical AND: output 1 hai sirf tab jab dono inputs 1 hon
• jab enable = 1: gated_clk clk ko copy karta hai (ticks pass through) → block normally chalta hai
• jab enable = 0: gated_clk low par stuck hai (flat line) → clock toggling band → $\alpha =0$

AND kyun, aur clock line kyun? Clock synchronous logic mein har flip ka source hai. Clock ki toggling band karo aur har downstream bucket freeze ho jaata hai — aap poore block ko ek gate se disable kar dete ho. AND naturally "sirf tab pass-through jab allowed ho" gate hai.

TASVEER. Left half: enable = 1, gated clock ek clean square wave hai. Right half: enable = 0, gated clock flat ho jaati hai. Frozen region mein $\alpha =0$ hai.

Clock tree mein yeh enables kahaan baithte hain, iske liye Hierarchical Clock Distribution dekhein.

---

Step 5 — Glitch trap (ek degenerate case)

KYA HAI. Ek naive AND mein ek hidden failure hai. Agar enable 1 se 0 par jabki clk abhi bhi high hai gir jaata hai, to AND output mid-pulse gir jaata hai. Woh short flat-phir-fall ek extra clock edge ki tarah lagta hai — ek glitch — aur galat tarike se ek flip-flop ko trigger kar sakta hai.

Yeh kyun fail karta hai. AND apne inputs ko instantly maan leta hai. Usse koi idea nahi ki jo "1" already in flight hai use finish hona chahiye. Isliye mid-pulse enable change pulse shape corrupt kar deta hai.

FIX. Ek latch daalo jo clock ke falling edge par enable sample karta hai, taaki AND sirf woh enable dekhe jo tab badla jab clk = 0 tha. Ab enable high phase ke dauran guaranteed stable hai → koi glitch nahi.

TASVEER. Top trace: raw enable mid-high gir raha hai — AND ek jagged glitch produce karta hai (red). Bottom trace: latched enable, jo sirf tab move karta hai jab clk low hai — clean pulses (green).

---

Step 6 — Clock gating ek bar kyun chhod jaati hai: leakage

KYA HAI. Clock freeze karo aur $P_{\text{dyn}}=0$ — lekin Step 1 ka bottom bar bachta hai. Jab tak $V_{\text{dd}}$ connected hai, transistors ek chhota sa subthreshold current $I_{\text{leak}}$ leak karte hain jab "off" bhi hote hain.

Ab yeh kyun matter karta hai. Deep-submicron nodes (7 nm) mein, yeh trickle total power ka 30–40% ho sakti hai. Clock gating ise kabhi nahi touch karti — kyunki $V_{\text{dd}}$ abhi bhi wahan hai. Leakage ko khatam karne ke liye aapko $V_{\text{dd}}$ par hi attack karna hoga.

TASVEER. Step-1 bar chart teen baar repeat: full block; clock-gated (top pile gone, bottom pile remains); arrow us stubborn bottom bar ki taraf point karta hai jise hum abhi bhi remove karna chahte hain.

---

Step 7 — Power gating: rail hi kaat do

KYA HAI. Rail ke saath series mein ek bada transistor switch lagao. Block ke upar ek PMOS ek header switch hai; neeche ek NMOS ek footer switch hai. Ek sleep signal ise kholta hai.

• sleep = 0 → switch closed → block $V_{\text{dd}}$ dekhta hai → normally chalta hai
• sleep = 1 → switch open → block disconnected → uske across voltage collapse → $I_{\text{leak}}\to 0$

Yeh kyun kaam karta hai. Leakage ko push karne ke liye voltage chahiye. Voltage hatao (rail kholo) aur dono dher gayab ho jaate hain: na dynamic power (koi rail nahi swing karne ke liye) aur na static power (koi rail nahi leak karne ke liye). Isliye power gating strictly zyada powerful — aur strictly zyada disruptive — hai clock gating se. Yeh Multi-Threshold CMOS se related hai, jahaan yeh switches high-threshold transistors use karte hain jo khud muskil se leak karte hain.

TASVEER. Ek header switch ke saath rail ek gate ki tarah drawn. Left: closed, block powered (green). Right: open, block dark, sirf ek tiny residual switch leak.

---

Step 8 — Cost: state loss aur wake-up (edge case)

KYA HAI. $V_{\text{dd}}$ kaat do aur har ordinary flip-flop apna bit bhool jaata hai. Aur rail wapas on karna instant nahi hota: bade switch ko block ke buckets charge karne mein time lagta hai, phir state restore karni padti hai.

Do remedies:

1. Save/restore karo state ko sone se pehle always-on memory mein.
2. Retention flip-flops — ek tiny always-on rail $V_{\text{ret}}$ par ek slave latch sleep ke through ek bit hold karta hai (dekhein Retention Flip-Flops).

Yeh deciding trade-off kyun hai. Power gating ek wake-up latency pay karta hai (roughly switch ke liye 10–100 ns plus restore ke liye ~100 ns, total ≈200 ns). Yeh tabhi jeet ta hai jab idle time us latency se zyada ho. Idle length predict karna OS, DVFS (Dynamic Voltage and Frequency Scaling) controller, ya Power Management IC (PMIC) ka kaam hai.

TASVEER. Ek timeline: block active, phir sleep asserted (dark), phir wake-up ramp (orange) phir se active hone se pehle. Sleep se pehle ek green "save" tick aur wake ke baad ek green "restore" tick.

---

Ek-tasveer ka summary

Yeh final figure poori walkthrough compress karta hai: Step 1 ke do power dher, aur har technique kahaan kaatti hai. Clock gating dynamic pile ko slice karti hai ($\alpha \to 0$ ke through); power gating dono piles ko slice karti hai ($V_{\text{dd}}\to 0$ ke through) wake-up time ki kimat par.

Recall Feynman retelling — seedha bolo

Ek chip do tarikon se power waste karta hai. Ek: har baar jab ek wire flip karta hai, tum charge ka ek chhota bucket bharte aur dump karte ho — yahi dynamic power hai, aur yeh scale hoti hai kitni baar cheezein flip karti hain usse. Do: jab kuch bhi flip nahi hota, tab bhi ek tiny current transistors ke through leak hoti rehti hai jab tak wall socket ($V_{\text{dd}}$) plugged in hai — yahi static power hai.

Clock gating waisi hai jaise ek rest kar rahi band ke liye metronome pause karna: clock ticks band karo aur flip-flops flipping band kar dete hain, toh flipping-bucket cost zero ho jaati hai. Lekin amp abhi bhi plugged in hai — leakage trickle karte rehti hai. Sasta, instant, koi memory loss nahi, chhoti breaks ke liye badiya. Bas latch yaad rakhna, warna ek fake beat (glitch) create ho jaayegi aur band confuse ho jaayegi.

Power gating amp ko bilkul unplug karna hai: koi rail nahi, toh kuch flip nahi hota aur kuch leak nahi hota — dono bars gone. Lekin band apna sheet music bhool jaati hai (state loss), aur wapas plug in karna aur music re-read karna real time leta hai (wake-up ~200 ns). Isliye aap tabhi unplug karte ho jab break itna lamba ho ki worth it ho, aur sheet music ko ek tiny always-on rail par ek retention latch mein safe rakhte ho.

Ek sentence: short idles ke liye $\alpha$ ghono, lambi idles ke liye $V_{\text{dd}}$ maro.

Recall Quick self-test

Clock gating kya zero par drive karta hai, aur kaun sa power pile bachta hai? ::: Yeh activity factor $\alpha \to 0$ drive karta hai, dynamic power khatam karta hai; static leakage pile bachti hai kyunki $V_{\text{dd}}$ abhi bhi connected hai. Bare-AND clock gate dangerous kyun hai? ::: Agar enable tab change ho jab clk high ho, to AND output mid-pulse gir jaata hai, ek glitch create karta hai (ek false clock edge); ek falling-edge latch ise fix karta hai. Register file 20% cycles mein use hoti hai, ungated $\alpha =0.5$ — dynamic power saved kitna? ::: ${\alpha }_{\text{eff}}=0.5\times 0.2=0.1$, isliye $(0.5-0.1)/0.5=80\%$ saved. Power gating ko retention flip-flops ki zaroorat kyun hai? ::: $V_{\text{dd}}$ katna ordinary flip-flops ko erase kar deta hai; always-on $V_{\text{ret}}$ rail par ek slave latch sleep ke across bit preserve karta hai.

---

Yeh kahaan connect karta hai