Dark silicon problem

The Physics Behind Dark Silicon

Power Density Crisis

The fundamental equations:

$P_{\text{dynamic}} = \alpha C V^2 f$

$P_{\text{static}} = V I_{\text{leak}}$

Where:

$\alpha$ = activity factor (fraction of transistors switching)
$C$ = capacitance
$V$ = supply voltage
$f$ = clock frequency
$I_{\text{leak}}$ = leakage current

Why Dennard scaling broke down:

Formula Dennard Scaling (1974-2005)

Classical Dennard scaling predicted that as transistors shrink by factor $s$ :

Dimensions: $\times \frac{1}{s}$
Voltage: $\times \frac{1}{s}$
Capacitance: $\times \frac{1}{s}$ (proportional to area)
Frequency: $\times s$ (inversely proportional to delay)

Result: Power density stays constant! $P_{\text{density}} = \frac{\alpha C V^2 f}{A} = \frac{\alpha \cdot \frac{C}{s} \cdot \frac{V^2}{s^2} \cdot s \cdot f}{\frac{A}{s^2}} = \frac{\alpha C V^2 f}{A}$

Why this step? The $s$ factors cancel: capacitance and voltage squared each drop by $s$ , frequency increases by $s$ , and area shrinks by $s^2$ . Everything balances.

But reality diverged around 65nm:

Voltage can't scale below $\sim$ 0.7V → transistors stop switching reliably (threshold voltage $V_t$ doesn't scale proportionally)
Leakage explodes → $I_{\text{leak}}$ grows exponentially as oxide thickness shrinks (quantum tunneling)
Power density increases → $P \propto f$ but $V$ is stuck, so $P$ grows with frequency

Quantifying Dark Silicon

Formula Dark Silicon Fraction

Given a chip with $N$ cores, power budget $P_{\text{TDP}}$ , and per-core power $P_{\text{core}}$ : $\text{Active cores} = \left\lfloor \frac{P_{\text{TDP}}}{P_{\text{core}}} \right\rfloor$

$\text{Dark silicon fraction} = 1 - \frac{P_{\text{TDP}}}{N \cdot P_{\text{core}}}$

Derivation from first principles:

Total available power across all cores: $N \cdot P_{\text{core}}$
Power we can actually deliver: $P_{\text{TDP}}$
Utilization fraction: $\frac{P_{\text{TDP}}}{N \cdot P_{\text{core}}}$
Dark fraction is what's left over: everything we can't power

Why this step? If TDP covers only 25% of total potential power draw, then 75% must stay dark.

Example evolution (Moore's Law continues, Dennard scaling stops):

| Year | Node | Cores | TDP (W) | Power/core (W) | Active | Dark % | |------|------|---------|-------------|--------|--------| | 2005 | 90nm | 2 | 100 | 50 | 2 | 0% | | 2010 | 45nm | 8 | 100 | 25 | 4 | 50% | | 2015 | 14nm | 32 | 100 | 12.5 | 8 | 75% | | 2020 | 7nm | 128 | 100 | 6.25 | 16 | 87.5% |

Why this matters: Every process generation, we double transistor count but TDP stays fixed (cooling limits). Dark silicon fraction approaches 100%.

Consequences and Trade-offs

Worked example Example 1: Many-Core vs. Accelerator Strategy

Scenario: 100W TDP chip, 16nm node. You can fit either:

Option A: 64 simple cores, 2W each when active
Option B: 8 general cores (5W each) + 4 specialized accelerators (10W each)

Analysis Option A:

Active cores: $\lfloor 100/2 \rfloor = 50$ cores max
Dark silicon: $(64-50)/64 = 21.9\%$
Good for: highly parallel workloads

Analysis Option B:

All 8 cores + 2 accelerators = $8(5) + 2(10) = 60$ W → fits!
Dark silicon: $(4(10)+8(5)-60)/(4(10)+8(5)) = 40/100 = 40\%$
Good for: specialized workloads (video, crypto, ML)

Why this step? Option B has higher dark silicon percentage but potentially better performance on target workloads—this is the key insight driving heterogeneous architectures.

Worked example Example 2: Dynamic Voltage-Frequency Scaling (DVFS)

Problem: Run a 4-core chip where each core at max frequency (3.5 GHz, 1.0V) consumes 30W, but TDP is 80W.

Without DVFS:

Can run: $\lfloor 80/30 \rfloor = 2$ cores
Dark: 2 cores (50%) With DVFS (reduce to 2.0 GHz, 0.8V):
Power scales: $P \propto V^2 f$ → $P' = 30\cdot (0.8^2) \cdot (2.0/3.5) = 30 \cdot 0.64 \cdot 0.571 \approx 11$ W
Can run: $\lfloor 80/11 \rfloor = 7$ cores… wait, we only have 4!
All 4 cores active at 44W total, 0% dark silicon Trade-off: Lower per-core performance (2.0 vs 3.5 GHz) but higher throughput (4 cores vs 2).

Why this step? Voltage scaling is quadratic, so dropping from 1.0V to 0.8V cuts power by 36%. Frequency scaling is linear. Together they enable full utilization at lower performance.

Worked example Example 3: Turbo Boost as Dark Silicon Management

Intel Turbo Boost logic:

Base all8 cores at 2.5 GHz (80W total, 10W each)
Turbo: if only 2 cores active, boost to 4.0 GHz (40W each, 80W total) Why it works: 6 cores go dark (powered off), their60W budget redistributed to 2 cores.

$P_{\text{turbo}} = P_{\text{TDP}} - (N_{\text{idle}} \cdot P_{\text{static}})$

Assuming $P_{\text{static}} \approx 1$ W per idle core: $P_{\text{turbo}} = 80 - 6(1) = 74\text{W for 2 cores} \approx 37\text{W each}$

At higher voltage (1.2V) and frequency (4.0 GHz): $P = \alpha C (1.2)^2 (4.0) \approx 37\text{W}$ Why this step? Turbo Boost is explicit dark silicon management: trade paralelism for single-thread performance by concentrating power budget.

Architectural Responses

The industry has adopted three main strategies:

Heterogeneous architectures (big.LITTLE, ARM DynamIQ)
- Mix high-performance and power-efficient cores
- Schedule tasks to appropriate core types
- Example: Apple M-series (performance + efficiency cores)
Specialized accelerators (GPU, TPU, neural engines)
- Fixed-function units for specific domains
- 10-100× better performance-per-watt than general cores
- Dark silicon when not in use, but massive wins when active
Dynamic resource management
- DVFS: adjust voltage/frequency per-core
- Power gating: completely shut off unused regions
- Thread migration and load balancing

Common mistake Common Misconception: "Just Add More Cores"

Wrong reasoning: Moore's Law still works, so doubling cores every 2 years will double performance.

Why it feels right: Historically (1990s-2005), more transistors = more performance. We're conditioned to expect this scaling.

The reality: $\text{Performance} \propto \text{Active cores} = \frac{P_{\text{TDP}}}{P_{\text{core}}}$

If $P_{\text{TDP}}$ is fixed and $P_{\text{core}}$ doesn't scale down (Dennard breakdown), active cores stays constant even as total core count grows. You get:

More transistors (Moore's Law ✓)
Same active cores (Dark silicon ✗)
No performance gain from extra cores

The fix: Performance growth now requires:

Better algorithms/software (Amdahl's Law matters more)
Heterogeneous designs (right core for right task)
Specialization (accelerators for common operations)
Reduced voltage operation (sacrifice frequency for efficiency)

Connections to Other Topics

Dennard-scaling — the breakdown that causes dark silicon
Mores-law — provides transistors we can't fully utilize
TDP-and-power-budget — the constraint that creates darkness
Amdahls-law — limits software paralelism, making dark silicon worse
Heterogeneous-computing — architectural response to dark silicon
DVFS — technique to manage dark silicon dynamically
Power-gating — method to reduce leakage in dark regions
Multi-corescaling — why adding cores has diminishing returns

Recall Explain It to a 12-Year-Old

You know how when you get a big box of crayons, like the 64-pack? You have all these colors, but if you try to use them all at once, your hand gets tired and hot from coloring so fast, right?

Computer chips are the same way! Engineers can make chips with hundreds of "cores" (like tiny computers inside). But here's the catch: if you try to run all of them at full speed at the same time, the chip gets WAY too hot—hot enough to break itself!

So even though you have 100 cores, you might only be able to turn 25 of them at once. The other 75 have to sit there doing nothing, staying "dark" and turned off. That's dark silicon—it's like having crayons you paid for but can't use because your hand would catch on fire.

Why does this happen? Old computers could get more powerful by making everything smaller AND using less electricity. But about 20 years ago, the "using less electricity" part stopped working. Now we can make things smaller (more crayons in the box!), but each crayon still uses the same electricity. So we run out of power budget before we run out of crayons to use.

Active Recall Flashcards

#flashcards/hardware

What is dark silicon? :: The fraction of a chip's transistors that must be powered off at any given time due to power and thermal constraints, despite being physically present and functional.

Why did dark silicon emerge as a problem?

Dennard scaling broke down (~2005) so power density no longer stayed constant with shrinking transistors. Voltage couldn't scale below ~0.7V and leakage current exploded, meaning TDP stayed fixed while transistor count continued to grow (Moore's Law).

What is the formula for dark silicon fraction?

Dark fraction = 1 - (P_TDP)/(N × P_core), where N is total cores, P_TDP is thermal design power, and P_core is power per core when active.

How does dynamic power scale with voltage and frequency?

P_dynamic = α C V² f, where the voltage dependence is quadratic (V²) and frequency dependence is linear (f).

Why did Dennard scaling predict constant power density?

As dimensions shrank by factor s, capacitance and voltage each dropped by s (voltage squared by s²), frequency increased by s, and area dropped by s². The factors canceled: P/A stayed constant.

What are three main architectural responses to dark silicon?

1) Heterogeneous architectures (big.LITTLE cores), 2) Specialized accelerators (GPUs, TPUs), 3) Dynamic resource management (DVFS, power gating).

How does Turbo Boost relate to dark silicon?

Turbo Boost deliberately creates dark silicon by powering off some cores to concentrate the power budget on fewer cores, allowing them to run at higher voltage and frequency for better single-thread performance.

Why can't voltage scale below ~0.7V? :: Below this threshold, transistors become unreliable due to threshold voltage (Vt) limits—they can't distinguish between on/off states clearly, leading to logical errors.

What is the difference between dynamic and static power?

Dynamic power (αCV²f) is consumed when transistors switch state. Static power (V×I_leak) is consumed continuously due to leakage current, even when transistors aren't switching. Static power has grown to 30-50% of total power at modern nodes.

If a chip has 64 cores, 100W TDP, and each core needs 2W when active, what is the dark silicon percentage?

Active cores = ⌊100/2⌋ = 50. Dark silicon = (64-50)/64 = 14/64 = 21.875%.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dark siliconek bahut badi problem hai modern processors mein. Sochiye, ap ek building bana sakte ho jismein 100 offices hain, lekin apka power connection sirf 25 offices ko ek sath electricity de sakta hai. Baki 75 offices toh bane hue hain, functional bhi hain, par use nahi kar sakte kyunki power budget limited hai. Yahi situation hai dark silicon ki.

Pehle zamane mein jab Dennard scaling kaam kar raha tha (1974-2005 tak), tab sab smootha. Transistors chhote hote gaye toh voltage bhi kam ho gaya, power density constant raha. Par2005 ke bad voltage 0.7V se neeche nahi ja sakta (transistor hi kaam karna band kar dega), aur leakage current bhi exponentially badh raha hai nanometer scale par. Result? Power density badh gayi, TDP (Thermal Design Power) fixed rahi, par transistor count Moore's Law ke hisaab se double hota raha. Toh ab aapke pas bahut sare cores hain par unhe simultaneously chala nahi sakte.

Industry ne teen tarike nikale hain is problem ko handle karne ke liye: heterogeneous architectures (big.LITTLE type, jahan different power levels ke cores ho), specialized accelerators (GPU, TPU jo specific kaam ke liye efficient hai), aur dynamic management (DVFS ya power gating se voltage-frequency adjust karo runtime par). Intel ka Turbo Boost bhi ek example hai—deliberately kuch cores ko band kar do taki b cores kozyada power mil sake aur wo fast chalen. Dark silicon ab architectureur software dono levels par innovation mang raha hai.