Dark silicon problem: Question bank — Hardware deep dive

Before we start, every symbol used below earns its meaning so nothing is a mystery.

Definition Every symbol on this page, in words

$α$ — the activity factor: the fraction of transistors actually flipping 0↔1 each clock tick. $α = 1$ means all switch; $α = 0$ means none do.
$C$ — the capacitance being charged and discharged when transistors switch; think of it as the size of the tiny "bucket" of charge each gate must fill.
$V$ — the supply voltage feeding the transistors.
$f$ — the clock frequency (switches per second).
$I_{leak}$ — the leakage current per transistor described above.
$P_{dynamic}$ — the dynamic power: watts burned by transistors actively switching, given below by $α C V^{2} f$ .
$P_{static}$ — the static (leakage) power: watts burned even when nothing switches, equal to $V I_{leak}$ summed over the transistors involved.
$N$ — the total number of cores physically on the chip.
$P_{core}$ — the power one core draws when active (built up from the symbols above just below).
$⌊ \cdot ⌋$ — the floor function: round down to the nearest whole number, because you cannot run a fractional core.

Related builds live in Dennard-scaling, Mores-law, TDP-and-power-budget, DVFS, Power-gating, Heterogeneous-computing, Amdahls-law and Multi-corescaling.

Reading the figure: the horizontal axis is process generation (2005→2020); the vertical axis is the number of cores on a log-base-2 scale (each gridline is a doubling). The cyan bars show the total cores the transistor budget provides (Moore's Law — 2, 8, 32, 128). The shorter amber bars, drawn in front, show how many of those cores the fixed TDP can actually power (2, 4, 8, 16). The cyan-minus-amber gap, labelled "dark", is the dark silicon: 0 cores in 2005 rising to 112 cores by 2020. Same watts, ever more idle transistors.

True or false — justify

Dark silicon means those transistors are broken or defective.

False. They are fully functional; they are simply not allowed on at the same time because the shared power/heat budget can't feed them all — like owning 16 burners but a breaker that trips past 4.

If Dennard scaling had never broken, we would still have a dark silicon problem.

False. Under working Dennard scaling, power-per-core shrinks exactly as fast as core count grows, so total power stays flat and every core can stay on. Dark silicon is a symptom of Dennard's breakdown.

Moore's Law dying is what caused dark silicon.

False — it's the opposite. Mores-law is still (mostly) alive: we keep getting more transistors. Dark silicon exists because Moore lives but Dennard-scaling died — we get the transistors but can't power them.

A chip at 0% dark silicon is always the best-designed chip.

False. 0% dark just means every transistor fits under TDP, often because there are few cores or they run slow. A chip with high dark fraction but powerful accelerators can crush it on real workloads — e.g. a heterogeneous mix of few general cores plus accelerators may show higher dark fraction yet win on target workloads (video, ML) via Heterogeneous-computing.

Dark silicon consumes no power because it is switched off.

False. "Off" here usually means "not switching," so

P_{dynamic} = 0

, but the transistors still leak

P_{static} = V I_{leak}

. Only true Power-gating (cutting the voltage supply) removes leakage, and even that is imperfect.

Lowering voltage saves more power than lowering frequency by the same fraction.

True. Dynamic power is

P_{dynamic} = α C V^{2} f

. Halve

V

: the

V^{2}

term becomes

\frac{1}{4}

, so power drops to a quarter. Halve

f

instead: power only halves. So a 20% voltage cut saves ~36% (

1 - 0. 8^{2}

) while a 20% frequency cut saves only 20%.

Turbo Boost violates the TDP ceiling to go faster.

False. Turbo stays under TDP. It parks most cores (frees their budget) and hands that freed power to the 1–2 active cores, so single-thread speed rises without breaking the ceiling.

Doubling the number of cores each generation doubles performance.

False. Performance

\propto

active cores

= ⌊ P_{TDP} / P_{core} ⌋

. If

P_{core}

stops shrinking (Dennard's end), active cores stay flat even as total cores

N

double — you gain dark silicon, not speed.

Static (leakage) power got worse at smaller nodes.

True. As oxide layers thinned, electrons quantum-tunnel through them, so

I_{leak}

rose sharply and with it

P_{static} = V I_{leak}

. At 7nm/5nm, leakage can be 30–50% of total power.

Supply voltage can keep scaling down forever to save power.

False. Below roughly

0.7 V

the supply voltage

V

nears the transistor's threshold voltage

V_{t}

, and switching becomes slow and unreliable. This voltage floor is a core reason Dennard scaling stalled.

Spot the error

"We have 128 cores and 100W TDP with 6.25W per core, so all 128 run at once."

Error: active cores

= ⌊ 100/6.25 ⌋ = 16

, not 128. The other 112 must stay dark — that's

87.5%

dark silicon.

"Power density

= α C V^{2} f / A

(per unit area

A

); when transistors shrink, the density rises, so scaling always heats chips."

Error: under ideal Dennard scaling the factors cancel. Let one generation shrink linear size by

s > 1

, so

C \to C / s

V \to V / s

(hence

V^{2} \to V^{2} / s^{2}

), and area

A \to A / s^{2}

. Frequency rises to

s f

because a smaller transistor switches in

1/ s

of the time — a gate that flips

s

times faster runs at

s

times the clock. Then

\frac{α ( C / s ) ( V ^{2} / s ^{2} ) ( s f )}{A / s ^{2}} = \frac{α C V ^{2} f}{A}

— density is constant. It rose only because

V

got stuck (couldn't drop by

s

) while

f

kept climbing — a breakdown, not the rule.

"DVFS lets you run 7 cores on a 4-core chip because

⌊ 80/11 ⌋ = 7

Error: the formula gives a ceiling of 7, but you can't run more cores than the

N = 4

you physically have. The real result is all 4 cores active (

4 \times 11 = 44

< 80

W TDP), i.e. 0% dark.

"Accelerators are wasteful — they sit dark most of the time."

Error framing: sitting dark is fine because their leakage

P_{static}

is small when gated. When active they deliver 10–100× better performance-per-watt, which is precisely how Heterogeneous-computing spends a fixed budget well.

"Since dark regions are off, we can ignore them in the thermal model."

Error: dark transistors still burn

P_{static} = V I_{leak}

each, so a region of them adds real heat. Ignoring this static power under-estimates temperature and can trip thermal throttling.

"Power gating is free — just cut the supply and instantly wake it back up."

Error: Power-gating zeroes

P_{static}

, but waking the region back re-charges its capacitance

C

and takes on the order of

1 0^{2}

nanoseconds to milliseconds — a measurable latency and energy cost, not zero.

Why questions

Why does a fixed TDP, not transistor count, decide how many cores can run?

Because heat removal is the true bottleneck:

P_{TDP}

is the wattage the cooler can carry away. Transistors are cheap and plentiful; watts of sustained heat are the scarce, capped resource.

Why does specialization (Heterogeneous-computing, accelerators) help against dark silicon rather than just adding more general cores?

A general core spends many watts to do a task an accelerator does in a fraction of the energy. Getting more work per watt means more of the fixed budget turns into useful results, even if the accelerator is dark when idle.

Why does Amdahls-law matter more now than it did in the Dennard era?

When you can't just add active cores for free, remaining speedups must come from software parallelism — and Amdahl's Law caps how much a serial fraction can benefit, making algorithmic efficiency the new frontier.

Why is voltage scaling the first lever DVFS reaches for?

Because

P_{dynamic}

depends on

V^{2}

: a small voltage drop yields a large, quadratic power saving, letting more cores fit under TDP. Frequency

f

is reduced alongside because a lower voltage can't sustain the high frequency.

Why can Turbo Boost make a laptop feel fast on a single app but not on a heavy multithreaded one?

Turbo concentrates the whole freed budget into 1–2 cores for single-thread bursts. With all cores loaded, there is no idle budget to redistribute, so each core stays near base clock.

Why does the dark silicon fraction creep toward 100% each generation?

Core count

N

doubles (Moore) while

P_{TDP}

is held flat by cooling limits and

P_{core}

barely drops (Dennard broken). So the ratio

P_{TDP} / (N \cdot P_{core})

shrinks every node, and dark fraction

= 1 -

that ratio rises.

Edge cases

A single-core chip whose one core draws less than TDP — what is its dark silicon fraction?

0%. With

N = 1

and

P_{core} \leq P_{TDP}

, the ratio

P_{TDP} / (N P_{core}) \geq 1

, so nothing must be dark (fraction is clamped at 0, never negative).

The dark fraction formula gives a negative number — what does that mean?

It means

P_{TDP}

exceeds total possible core draw

N \cdot P_{core}

, so all cores fit and there is spare budget. A negative result is physically read as 0% dark (and possibly headroom for DVFS or turbo).

A single core whose power draw exceeds the whole TDP — what happens?

⌊ P_{TDP} / P_{core} ⌋ = 0

: zero cores can run at that voltage/frequency, so the chip is effectively 100% dark. The only escape is DVFS — drop

V

and

f

until one core's power falls under TDP.

What happens to dark silicon if you increase TDP (bigger heatsink, liquid cooling)?

More budget means more active cores, so dark fraction falls. But TDP can't grow without limit — heat removal and hot-spot temperature eventually cap it, which is why cooling alone can't cancel dark silicon.

A chip where every core is power-gated off — is any power consumed?

Nearly zero, since gating drives

P_{static} \to 0

and

P_{dynamic} = 0

. But some always-on control logic keeps a small residual draw, so "fully off" is an approximation, not a true zero.

At the exact TDP boundary where

P_{TDP}

is an integer multiple of

P_{core}

, how many cores run?

Exactly

P_{TDP} / P_{core}

cores, since the floor of an integer is itself — the last core just fits with zero headroom, leaving no slack for turbo or variation.

If per-core power dropped by half each generation (Dennard restored), what happens to dark silicon as cores double?

It stays flat at its current level. Doubling

N

while halving

P_{core}

keeps

N \cdot P_{core}

constant, so the same TDP powers the same fraction — the very balance that kept early chips at 0% dark.

Recall Fast self-test

Dark silicon exists because Moore ___ and Dennard ___. ::: lives (more transistors) / died (can't power them all). The lever DVFS pulls first, and why. ::: Voltage $V$ , because $P_{dynamic}$ scales as $V^{2}$ (quadratic saving). The reason "off" cores still cost power. ::: Leakage keeps $P_{static} = V I_{leak}$ flowing until true power-gating cuts the supply.