Dark silicon problem: Worked examples — Hardware deep dive

This page is a worked-example gym for the Dark silicon problem. We take the two power laws and the dark-silicon formula and push them through every kind of case: the easy one, the zero cases, the degenerate cases, the "it goes negative — what does that mean?" cases, and the limiting case as chips grow forever.

Before any numbers, let us re-anchor the three tools we will use, so no symbol appears unexplained.

The scenario matrix

Every dark-silicon question falls into one of these cells. Each worked example is tagged with the cell(s) it covers.

Cell	Case class	What's special about it	Example
A	Ordinary case	Budget covers some cores; $0 < D < 1$	Ex 1
B	Zero dark silicon	Budget covers all cores; $D = 0$ exactly	Ex 2
C	Fully dark limit	$N \to \infty$ , budget fixed; $D \to 1$	Ex 3
D	Degenerate input	$P_{core} \to 0$ or $N = 1$	Ex 4
E	Sign / trade-off	Same budget, two configs — which "sign" of choice wins	Ex 5
F	Over-budget (negative $D$ )	Ratio $> 1$ ; $D < 0$ — interpret it	Ex 6
G	Real-world word problem	DVFS rescues utilization	Ex 7
H	Exam twist	Turbo Boost: redistribute a fixed budget	Ex 8

Figures accompany the geometric/graphical cells (A, C, G).

Worked example Ex 1 — Cell A: the ordinary case

A 14 nm chip has $N = 32$ cores, each active core draws $P_{core} = 12.5$ W, and the cooling budget is $P_{TDP} = 100$ W. Find the active-core count and the dark silicon fraction.

Forecast: Guess before reading — will $D$ be closer to $\frac{1}{4}$ , $\frac{1}{2}$ , or $\frac{3}{4}$ ?

Active cores $= ⌊ \frac{P _{TDP}}{P _{core}} ⌋ = ⌊ \frac{100}{12.5} ⌋ = ⌊ 8 ⌋ = 8$ . Why this step? Each active core eats $12.5$ W; you keep switching cores on until the next one would break the $100$ W budget. The floor $⌊ \cdot ⌋$ is there because you cannot run "0.7 of a core".
Dark fraction $D = 1 - \frac{P _{TDP}}{N \cdot P _{core}} = 1 - \frac{100}{32 \times 12.5} = 1 - \frac{100}{400} = 0.75$ . Why this step? $32 \times 12.5 = 400$ W is the power all cores together would draw; you're allowed only $100$ W, i.e. one quarter — so three quarters must stay dark.

Verify: $8$ active out of $32$ present is $8/32 = 0.25$ lit, hence $0.75$ dark — matches $D$ . Units: watts cancel in the ratio, so $D$ is dimensionless. ✓ ( $D = 75%$ .)

Worked example Ex 3 — Cell C: the fully-dark limit

Keep $P_{TDP} = 100$ W and $P_{core} = 6.25$ W fixed. Let core count double every generation: $N = 2, 8, 32, 128, \dots$ . What does $D$ approach?

Forecast: Does $D$ climb toward some ceiling, or grow without bound?

Write $D (N) = 1 - \frac{100}{6.25 N} = 1 - \frac{16}{N}$ . Why this step? $100/6.25 = 16$ is the fixed number of cores the budget can ever light — it does not grow with $N$ .
Evaluate: $N = 32 \Rightarrow D = 1 - \frac{16}{32} = 0.5$ ; $N = 128 \Rightarrow D = 1 - \frac{16}{128} = 0.875$ . Why this step? Moore's law grows $N$ (Mores-law) but the "16 lit cores" ceiling is stuck, so the fraction lit shrinks.
Limit: as $N \to \infty$ , $\frac{16}{N} \to 0$ , so $D \to 1$ . Why this step? Sixteen lit cores out of a billion is essentially zero fraction lit — the chip is almost entirely dark. This is the core prophecy of the dark-silicon problem.

Verify: $D (128) = 1 - 16/128 = 1 - 0.125 = 0.875 = 87.5%$ — matches the 7 nm row of the parent table. Curve is monotonically rising toward the horizontal asymptote $D = 1$ . ✓

Worked example Ex 4 — Cell D: degenerate inputs

Test the formula at its edges. (a) $N = 1$ . (b) $P_{core} \to 0$ .

Forecast: Does the formula stay sane, or blow up?

(a) Single core, budget $P_{TDP} = 100$ W, $P_{core} = 50$ W: $D = 1 - \frac{100}{1 \times 50} = 1 - 2 = - 1.$ Why this step? One core wanting $50$ W under a $100$ W budget can obviously always run — there is nothing to leave dark. A negative $D$ is the formula's way of screaming "you have surplus budget" (this bridges to Cell F). We clamp it: physically $D = max (0, formula) = 0$ .
(b) Vanishing per-core power: as $P_{core} \to 0^{+}$ , $D = 1 - \frac{P _{TDP}}{N \cdot P _{core}} \to 1 - (+ \infty) \to - \infty.$ Why this step? If a core costs almost nothing, the budget lights arbitrarily many — surplus is unbounded, so the raw formula dives to $- \infty$ . Clamped: $D = 0$ . A "free" transistor is never forced dark.

Verify: Both degenerate cases give surplus $\Rightarrow$ clamped $D = 0$ , which is exactly what physical intuition demands. The clamp rule $D = max (0, 1 - \frac{P _{TDP}}{N P _{core}})$ handles them. ✓

Worked example Ex 5 — Cell E: the sign of the trade-off (many-core vs accelerator)

$100$ W, 16 nm. Option A: $64$ simple cores at $2$ W each. Option B: $8$ general cores ( $5$ W) $+ 4$ accelerators ( $10$ W). Which has more dark silicon — and does that mean it's worse?

Forecast: Guess which option is "darker", then whether darker = worse.

Option A active cores $= ⌊ 100/2 ⌋ = 50$ out of $64$ . $D_{A} = \frac{64 - 50}{64} = \frac{14}{64} = 0.21875$ . Why this step? Uniform cores, so we can count them directly; $50$ lit, $14$ dark.
Option B total wanted power $= 8 (5) + 4 (10) = 40 + 40 = 80$ W of general+accelerator silicon exists. Under $100$ W budget, we can run $8$ cores $+ 2$ accelerators $= 40 + 20 = 60$ W (assume you run all 8 cores and boot accelerators until budget-safe). $D_{B} = \frac{( 40 + 40 ) - 60}{40 + 40} = \frac{20}{80} = 0.25$ . Why this step? Here "dark" is measured in watts of capability left unpowered, not just cores, because the units are heterogeneous (Heterogeneous-computing).
Interpret the sign of the choice: $D_{B} = 25% > D_{A} = 21.875%$ , yet Option B may win on a video/ML workload because an accelerator does $10 \times$ the useful work per watt of a plain core. Why this step? Higher dark fraction is not automatically worse — the metric that matters is useful work per watt, not fraction lit.

Verify: $14/64 = 0.21875$ ✓; $20/80 = 0.25$ ✓. So $D_{B} > D_{A}$ numerically, confirming the counter-intuitive lesson driving accelerator designs. ✓

Worked example Ex 6 — Cell F: over-budget, negative

$D$ A niche chip: $N = 4$ cores, $P_{core} = 15$ W, $P_{TDP} = 100$ W. Compute the raw $D$ and interpret its sign.

Forecast: All four cores draw $4 \times 15 = 60$ W $< 100$ W. What does the formula report?

Raw formula: $D = 1 - \frac{100}{4 \times 15} = 1 - \frac{100}{60} = 1 - 1.6 \overline{6} = - 0.6 \overline{6}$ . Why this step? The ratio $100/60 > 1$ means the budget exceeds total draw — pure surplus of $40$ W.
Physical clamp: $D = max (0, - 0.667) = 0$ . No core is forced dark; the extra $40$ W could feed DVFS boosting or simply go unused. Why this step? Negative dark silicon is not a thing — it is budget headroom. The magnitude $∣ D ∣ \cdot N P_{core} = 0.667 \times 60 = 40$ W recovers exactly the surplus.

Verify: Surplus $= 100 - 60 = 40$ W. And $- D \times N P_{core} = 0.6 \overline{6} \times 60 = 40$ W — the negative value literally measures the headroom. Clamped $D = 0$ . ✓

Worked example Ex 7 — Cell G: real-world word problem (DVFS rescue)

A 4-core chip. Each core at $3.5$ GHz, $1.0$ V draws $30$ W. $P_{TDP} = 80$ W. First find dark silicon without DVFS. Then drop every core to $2.0$ GHz, $0.8$ V and recompute.

Forecast: Can we go from "2 cores dark" to "0 cores dark" just by turning voltage/frequency knobs?

No DVFS: active $= ⌊ 80/30 ⌋ = 2$ cores of $4$ . Dark $= (4 - 2) /4 = 0.5$ . Why this step? Two cores at $30$ W $= 60$ W fits under $80$ W; a third would hit $90$ W $> 80$ W.
Scale the power. Dynamic power obeys $P \propto V^{2} f$ . New power per core: $P^{'} = 30 \times (\frac{0.8}{1.0})^{2} \times \frac{2.0}{3.5} = 30 \times 0.64 \times 0.5714 \dots \approx 10.97 W .$ Why this step? Voltage enters squared ( $V^{2}$ ) so dropping $1.0 \to 0.8$ V multiplies by $0.64$ — a big cut. Frequency enters linearly, giving the $2.0/3.5$ factor. This is why DVFS lowers voltage and frequency together.
Recount: active $= ⌊ 80/10.97 ⌋ = 7$ — but only $4$ cores exist, so all 4 run, drawing $4 \times 10.97 \approx 43.9$ W. Dark $= 0$ . Why this step? Once the arithmetic says you can light more cores than you own, you cap at $N$ and dark silicon vanishes.

Verify: $30 \times 0.64 \times (2/3.5) = 10.971 \dots$ W ✓. $4 \times 10.971 = 43.9$ W $\leq 80$ W ✓, so $D = 0$ . Trade-off: per-core speed fell from $3.5$ to $2.0$ GHz, but throughput rose from $2$ to $4$ cores. ✓

Worked example Ex 8 — Cell H: exam twist (Turbo Boost redistribution)

An 8-core chip, base $2.5$ GHz, each core $10$ W, $P_{TDP} = 80$ W (all 8 fit exactly). A workload uses only 2 cores; the other 6 are power-gated (Power-gating) but each still leaks $P_{static} = 1$ W. How much power can each active core turbo up to?

Forecast: With 6 cores mostly off, how much of their freed budget can 2 cores grab?

Budget freed by idling 6 cores, minus their unavoidable leakage: $P_{turbo total} = P_{TDP} - N_{idle} \cdot P_{static} = 80 - 6 (1) = 74 W .$ Why this step? Power-gated cores still leak $1$ W each (this is the leakage-power lesson from the parent's second mistake box), so you can't reclaim the full $60$ W — only $60 - 6 = 54$ W of it is truly freed on top of the 2 cores' original $20$ W.
Per active core: $74/2 = 37$ W each. Why this step? Two cores split the $74$ W budget evenly, jumping from $10$ W to $37$ W — that extra headroom is spent raising voltage ( $\sim 1.2$ V) and frequency ( $\sim 4.0$ GHz).
Consistency with $P \propto V^{2} f$ : if $10$ W bought $(1.0 V, 2.5 GHz)$ , then scaling to $(1.2 V, 4.0 GHz)$ predicts $P = 10 \times (\frac{1.2}{1.0})^{2} \times \frac{4.0}{2.5} = 10 \times 1.44 \times 1.6 = 23.04 W .$ Why this step? The physics-scaled estimate ( $\approx 23$ W) is below the $37$ W budget, so the boost is thermally safe — the exam-safe answer is "up to $\approx 37$ W available, physics uses $\approx 23$ W of it." Turbo is explicit dark-silicon management: trade parallelism for single-thread speed.

Verify: $80 - 6 (1) = 74$ W ✓; $74/2 = 37$ W per core ✓; scaled draw $10 \times 1.44 \times 1.6 = 23.04$ W $\leq 37$ W ✓ (safe). This connects to Amdahls-law: turbo helps the serial fraction that can't be parallelised. ✓

Recall Which cell forces a

clamp, and why? Cells D and F ::: whenever the raw formula gives $D < 0$ , the budget exceeds total core draw, so physically no core is dark — clamp $D = max (0, formula)$ ; the negative magnitude measures surplus watts.

Recall Higher dark-silicon fraction always means worse chip. True or false?

False ::: Ex 5 — an accelerator config (Option B, $D = 25%$ ) can beat a uniform config (Option A, $D = 21.875%$ ) because useful-work-per-watt, not fraction lit, is what matters.

Connections

Dark silicon problem — the parent topic this gym drills
Dennard-scaling · Mores-law · TDP-and-power-budget — the three forces in the formula
DVFS · Power-gating · Heterogeneous-computing · Multi-corescaling — the rescue strategies used in Ex 5–8
Amdahls-law — why single-thread turbo (Ex 8) still matters