Dark silicon problem: Worked examples — Hinglish deep dive

6.4.7 · D3 · Hardware › Power, Thermal & Reliability › Dark silicon problem

Ye page Dark silicon problem ke liye ek worked-example gym hai. Hum do power laws aur dark-silicon formula leke har tarah ke case mein push karte hain: easy wala, zero cases, degenerate cases, "ye negative ho gaya — iska matlab kya hai?" wale cases, aur limiting case jab chips forever badhti jaati hain.

Koi bhi number dekhne se pehle, teen tools ko phir se anchor karte hain jo hum use karenge, taaki koi bhi symbol unexplained na rahe.

Scenario matrix

Har dark-silicon question inhi cells mein se kisi ek mein aata hai. Har worked example us cell ke saath tagged hai jo wo cover karta hai.

Cell	Case class	Usme kya khaas hai	Example
A	Ordinary case	Budget kuch cores cover karta hai; $0 < D < 1$	Ex 1
B	Zero dark silicon	Budget saare cores cover karta hai; $D = 0$ exactly	Ex 2
C	Fully dark limit	$N \to \infty$ , budget fixed; $D \to 1$	Ex 3
D	Degenerate input	$P_{core} \to 0$ ya $N = 1$	Ex 4
E	Sign / trade-off	Same budget, do configs — choice ka kaunsa "sign" jeetega	Ex 5
F	Over-budget (negative $D$ )	Ratio $> 1$ ; $D < 0$ — interpret karo	Ex 6
G	Real-world word problem	DVFS utilization rescue karta hai	Ex 7
H	Exam twist	Turbo Boost: ek fixed budget redistribute karo	Ex 8

Geometric/graphical cells (A, C, G) ke saath figures hain.

Worked example Ex 1 — Cell A: ordinary case

Ek 14 nm chip mein $N = 32$ cores hain, har active core $P_{core} = 12.5$ W draw karta hai, aur cooling budget $P_{TDP} = 100$ W hai. Active-core count aur dark silicon fraction nikalo.

Forecast: Padhne se pehle guess karo — kya $D$ zyada $\frac{1}{4}$ , $\frac{1}{2}$ , ya $\frac{3}{4}$ ke kareeb hoga?

Active cores $= ⌊ \frac{P _{TDP}}{P _{core}} ⌋ = ⌊ \frac{100}{12.5} ⌋ = ⌊ 8 ⌋ = 8$ . Ye step kyun? Har active core $12.5$ W khaata hai; tum cores on karte rehte ho jab tak agla $100$ W budget nahi todta. Floor $⌊ \cdot ⌋$ isliye hai kyunki tum "0.7 of a core" nahi chala sakte.
Dark fraction $D = 1 - \frac{P _{TDP}}{N \cdot P _{core}} = 1 - \frac{100}{32 \times 12.5} = 1 - \frac{100}{400} = 0.75$ . Ye step kyun? $32 \times 12.5 = 400$ W wo power hai jo saare cores milke draw karte; tumhe sirf $100$ W allowed hai, yaani ek chauthai — to teen chauthai dark rehna padega.

Verify: $8$ active out of $32$ present yaani $8/32 = 0.25$ lit, isliye $0.75$ dark — $D$ se match karta hai. Units: ratio mein watts cancel ho jaate hain, isliye $D$ dimensionless hai. ✓ ( $D = 75%$ .)

Worked example Ex 3 — Cell C: fully-dark limit

$P_{TDP} = 100$ W aur $P_{core} = 6.25$ W fixed rakho. Core count har generation double ho: $N = 2, 8, 32, 128, \dots$ . $D$ kisi ceiling ki taraf jaata hai, ya unbounded badhta hai?

Forecast: Kya $D$ kisi ceiling ki taraf chadh jaata hai, ya bina bound ke badhta hai?

Likho $D (N) = 1 - \frac{100}{6.25 N} = 1 - \frac{16}{N}$ . Ye step kyun? $100/6.25 = 16$ wo fixed number of cores hain jo budget kabhi bhi light kar sakta hai — ye $N$ ke saath nahi badhta.
Evaluate karo: $N = 32 \Rightarrow D = 1 - \frac{16}{32} = 0.5$ ; $N = 128 \Rightarrow D = 1 - \frac{16}{128} = 0.875$ . Ye step kyun? Moore's law $N$ badhata hai (Mores-law) par "16 lit cores" ceiling stuck hai, isliye lit ka fraction shrink hota hai.
Limit: jab $N \to \infty$ , $\frac{16}{N} \to 0$ , isliye $D \to 1$ . Ye step kyun? Ek billion mein se sixteen lit cores essentially zero fraction lit hai — chip almost entirely dark hai. Ye dark-silicon problem ki core prophecy hai.

Verify: $D (128) = 1 - 16/128 = 1 - 0.125 = 0.875 = 87.5%$ — parent table ke 7 nm row se match karta hai. Curve monotonically upar chadh raha hai horizontal asymptote $D = 1$ ki taraf. ✓

Worked example Ex 4 — Cell D: degenerate inputs

Formula ko uske edges par test karo. (a) $N = 1$ . (b) $P_{core} \to 0$ .

Forecast: Kya formula sane rehta hai, ya blow up hota hai?

(a) Single core, budget $P_{TDP} = 100$ W, $P_{core} = 50$ W: $D = 1 - \frac{100}{1 \times 50} = 1 - 2 = - 1.$ Ye step kyun? Ek core jo $50$ W chahta hai $100$ W budget ke niche obviously hamesha chal sakta hai — dark rakhne ke liye kuch bhi nahi hai. Negative $D$ formula ka tarika hai chillane ka "tumhare paas surplus budget hai" (ye Cell F se connect hota hai). Hum ise clamp karte hain: physically $D = max (0, formula) = 0$ .
(b) Vanishing per-core power: jab $P_{core} \to 0^{+}$ , $D = 1 - \frac{P _{TDP}}{N \cdot P _{core}} \to 1 - (+ \infty) \to - \infty.$ Ye step kyun? Agar ek core lagbhag kuch nahi cost karta, budget arbitrarily many light kar deta hai — surplus unbounded hai, isliye raw formula $- \infty$ ki taraf dive karta hai. Clamped: $D = 0$ . Ek "free" transistor kabhi dark rehne par majboor nahi hota.

Verify: Dono degenerate cases surplus dete hain $\Rightarrow$ clamped $D = 0$ , jo exactly physical intuition demand karta hai. Clamp rule $D = max (0, 1 - \frac{P _{TDP}}{N P _{core}})$ unhe handle karta hai. ✓

Worked example Ex 5 — Cell E: trade-off ka sign (many-core vs accelerator)

$100$ W, 16 nm. Option A: $64$ simple cores at $2$ W each. Option B: $8$ general cores ( $5$ W) $+ 4$ accelerators ( $10$ W). Kisme zyada dark silicon hai — aur kya darker matlab worse hai?

Forecast: Guess karo kaunsa option "darker" hai, phir socho darker = worse hai ya nahi.

Option A active cores $= ⌊ 100/2 ⌋ = 50$ out of $64$ . $D_{A} = \frac{64 - 50}{64} = \frac{14}{64} = 0.21875$ . Ye step kyun? Uniform cores hain, isliye directly count kar sakte hain; $50$ lit, $14$ dark.
Option B total wanted power $= 8 (5) + 4 (10) = 40 + 40 = 80$ W ka general+accelerator silicon exist karta hai. $100$ W budget ke niche, hum $8$ cores $+ 2$ accelerators $= 40 + 20 = 60$ W chala sakte hain (assume karo tum saare 8 cores chalate ho aur accelerators tab tak boot karte ho jab tak budget-safe ho). $D_{B} = \frac{( 40 + 40 ) - 60}{40 + 40} = \frac{20}{80} = 0.25$ . Ye step kyun? Yahan "dark" ko watts of capability mein measure kiya jaata hai jo unpowered rahi, sirf cores nahi, kyunki units heterogeneous hain (Heterogeneous-computing).
Choice ke sign ko interpret karo: $D_{B} = 25% > D_{A} = 21.875%$ , phir bhi Option B video/ML workload par jeet sakta hai kyunki ek accelerator plain core ke comparison mein per watt $10 \times$ zyada useful work karta hai. Ye step kyun? Zyada dark fraction automatically worse nahi hota — jo metric matter karta hai wo useful work per watt hai, fraction lit nahi.

Verify: $14/64 = 0.21875$ ✓; $20/80 = 0.25$ ✓. Isliye numerically $D_{B} > D_{A}$ , jo accelerator designs drive karne wale counter-intuitive lesson ko confirm karta hai. ✓

Worked example Ex 6 — Cell F: over-budget, negative

$D$ Ek niche chip: $N = 4$ cores, $P_{core} = 15$ W, $P_{TDP} = 100$ W. Raw $D$ compute karo aur uske sign ko interpret karo.

Forecast: Saare chaar cores $4 \times 15 = 60$ W $< 100$ W draw karte hain. Formula kya report karega?

Raw formula: $D = 1 - \frac{100}{4 \times 15} = 1 - \frac{100}{60} = 1 - 1.6 \overline{6} = - 0.6 \overline{6}$ . Ye step kyun? Ratio $100/60 > 1$ matlab budget total draw se zyada hai — pure $40$ W surplus.
Physical clamp: $D = max (0, - 0.667) = 0$ . Koi core dark rehne par majboor nahi; extra $40$ W DVFS boosting ke liye use ho sakta hai ya simply unused reh sakta hai. Ye step kyun? Negative dark silicon koi cheez nahi hoti — ye budget headroom hai. Magnitude $∣ D ∣ \cdot N P_{core} = 0.667 \times 60 = 40$ W exactly surplus recover karta hai.

Verify: Surplus $= 100 - 60 = 40$ W. Aur $- D \times N P_{core} = 0.6 \overline{6} \times 60 = 40$ W — negative value literally headroom measure karta hai. Clamped $D = 0$ . ✓

Worked example Ex 7 — Cell G: real-world word problem (DVFS rescue)

Ek 4-core chip. Har core $3.5$ GHz, $1.0$ V par $30$ W draw karta hai. $P_{TDP} = 80$ W. Pehle DVFS ke bina dark silicon nikalo. Phir har core ko $2.0$ GHz, $0.8$ V par drop karo aur recompute karo.

Forecast: Kya hum sirf voltage/frequency knobs ghumakar "2 cores dark" se "0 cores dark" ja sakte hain?

No DVFS: active $= ⌊ 80/30 ⌋ = 2$ cores of $4$ . Dark $= (4 - 2) /4 = 0.5$ . Ye step kyun? Do cores at $30$ W $= 60$ W, $80$ W ke niche fit hota hai; teesra $90$ W hit karega jo $> 80$ W hai.
Power scale karo. Dynamic power $P \propto V^{2} f$ obey karta hai. New power per core: $P^{'} = 30 \times (\frac{0.8}{1.0})^{2} \times \frac{2.0}{3.5} = 30 \times 0.64 \times 0.5714 \dots \approx 10.97 W .$ Ye step kyun? Voltage squared enter hota hai ( $V^{2}$ ) isliye $1.0 \to 0.8$ V drop karna $0.64$ se multiply karta hai — ek bada cut. Frequency linearly enter hoti hai, jo $2.0/3.5$ factor deta hai. Isliye DVFS voltage aur frequency dono saath giraata hai.
Recount: active $= ⌊ 80/10.97 ⌋ = 7$ — par sirf $4$ cores exist karte hain, isliye saare 4 chalte hain, $4 \times 10.97 \approx 43.9$ W draw karte hue. Dark $= 0$ . Ye step kyun? Ek baar jab arithmetic kahe ki tum jo cores own karte ho usse zyada light kar sakte ho, tum $N$ par cap karo aur dark silicon gayab ho jaata hai.

Verify: $30 \times 0.64 \times (2/3.5) = 10.971 \dots$ W ✓. $4 \times 10.971 = 43.9$ W $\leq 80$ W ✓, isliye $D = 0$ . Trade-off: per-core speed $3.5$ se $2.0$ GHz par giri, par throughput $2$ se $4$ cores ho gaya. ✓

Worked example Ex 8 — Cell H: exam twist (Turbo Boost redistribution)

Ek 8-core chip, base $2.5$ GHz, har core $10$ W, $P_{TDP} = 80$ W (saare 8 exactly fit hote hain). Ek workload sirf 2 cores use karta hai; baaki 6 power-gated hain (Power-gating) par har ek phir bhi $P_{static} = 1$ W leak karta hai. Har active core kitne power tak turbo up kar sakta hai?

Forecast: 6 cores mostly off hone se, unka kitna freed budget 2 cores grab kar sakte hain?

Budget freed 6 cores idle karne se, minus unka unavoidable leakage: $P_{turbo total} = P_{TDP} - N_{idle} \cdot P_{static} = 80 - 6 (1) = 74 W .$ Ye step kyun? Power-gated cores phir bhi $1$ W each leak karte hain (ye parent ke second mistake box ka leakage-power lesson hai), isliye tum poore $60$ W reclaim nahi kar sakte — sirf $60 - 6 = 54$ W hi truly freed hai 2 cores ke original $20$ W ke upar.
Per active core: $74/2 = 37$ W each. Ye step kyun? Do cores $74$ W budget evenly split karte hain, $10$ W se $37$ W tak jump karte hue — wo extra headroom voltage ( $\sim 1.2$ V) aur frequency ( $\sim 4.0$ GHz) badhane mein spend hoti hai.
Consistency with $P \propto V^{2} f$ : agar $10$ W ne $(1.0 V, 2.5 GHz)$ diya, tab $(1.2 V, 4.0 GHz)$ tak scale karna predict karta hai $P = 10 \times (\frac{1.2}{1.0})^{2} \times \frac{4.0}{2.5} = 10 \times 1.44 \times 1.6 = 23.04 W .$ Ye step kyun? Physics-scaled estimate ( $\approx 23$ W) $37$ W budget se niche hai, isliye boost thermally safe hai — exam-safe answer hai "up to $\approx 37$ W available, physics $\approx 23$ W use karta hai." Turbo explicit dark-silicon management hai: parallelism trade karo single-thread speed ke liye.

Verify: $80 - 6 (1) = 74$ W ✓; $74/2 = 37$ W per core ✓; scaled draw $10 \times 1.44 \times 1.6 = 23.04$ W $\leq 37$ W ✓ (safe). Ye Amdahls-law se connect karta hai: turbo us serial fraction ki help karta hai jo parallelise nahi ho sakti. ✓

Recall Kaunsa cell

clamp force karta hai, aur kyun? Cells D aur F ::: jab bhi raw formula $D < 0$ deta hai, budget total core draw se zyada hai, isliye physically koi core dark nahi — clamp karo $D = max (0, formula)$ ; negative magnitude surplus watts measure karta hai.

Recall Zyada dark-silicon fraction hamesha worse chip matlab hota hai. True ya false?

False ::: Ex 5 — ek accelerator config (Option B, $D = 25%$ ) ek uniform config (Option A, $D = 21.875%$ ) ko beat kar sakta hai kyunki useful-work-per-watt, fraction lit nahi, wo cheez hai jo matter karti hai.

Connections

Dark silicon problem — parent topic jiske liye ye gym drill hai
Dennard-scaling · Mores-law · TDP-and-power-budget — formula mein teen forces
DVFS · Power-gating · Heterogeneous-computing · Multi-corescaling — Ex 5–8 mein use hone wali rescue strategies
Amdahls-law — kyun single-thread turbo (Ex 8) abhi bhi matter karta hai