Dark silicon problem: Exercises — Hardware deep dive

Definition Every symbol in the power split — defined before use

A core burns power in two ways (from the parent note): $P = dynamic (switching) α C V^{2} f + static (leaking) V I_{leak}$

$α$ = activity factor — the fraction of transistors actually flipping this cycle (a pure number between $0$ and $1$ ). More flipping = more dynamic power.
$C$ = capacitance — how much charge the gates must be filled/emptied of each switch (measured in farads). Bigger circuits = bigger $C$ .
$V$ = supply voltage — the electrical "push" (volts). It appears squared in dynamic power, so it is the strongest lever.
$f$ = clock frequency — how many switching cycles per second (hertz). It appears linearly.
$I_{leak}$ = leakage current — the trickle of current that flows through a transistor even when it is not switching (amperes). This is what makes "dark" silicon still waste power.

Keep the ratios in mind: dynamic power scales as $V^{2} f$ — voltage squared, frequency linear. Every DVFS solution below re-derives from this same $P_{dynamic} = α C V^{2} f$ line.

Definition The parent's generation table (reproduced here so this page stands alone)

The parent note tracks a chip family under a fixed $P_{TDP} = 100 W$ while Moore's law keeps doubling transistors and Dennard scaling has stopped. This page refers back to these rows, so they are reproduced here:

Year	Node	Cores $N$	Power/core (W)	Active	Dark
2005	90 nm	2	50	2	0%
2010	45 nm	8	25	4	50%
2015	14 nm	32	12.5	8	75%
2020	7 nm	128	6.25	16	87.5%

Level 1 — Recognition

Exercise 1.1 (L1)

A chip has $N = 16$ cores. Its power budget lets exactly $4$ cores run at once. What is the dark silicon fraction, expressed as a percentage?

Recall Solution

Dark silicon = the fraction that must stay off = $\frac{16 - 4}{16} = \frac{12}{16} = 0.75 = 75%$ . Answer: $75%$ . This is the "16 burners, breaker for 4" picture from the parent note.

Exercise 1.2 (L1)

Which of the two power terms — dynamic $α C V^{2} f$ or static $V I_{leak}$ — keeps flowing even when a core is not switching (clock effectively idle, $f \to 0$ )?

Recall Solution

Set $f = 0$ : dynamic power $α C V^{2} f = 0$ . But static power $V I_{leak}$ still has voltage $V$ across the transistors, so current still leaks. The static term survives. This is exactly why "dark" silicon still wastes power — see the leakage mistake in the parent note.

Exercise 1.3 (L1)

Recall the two historical laws by filling in the blanks (cloze — each ==...== hides one answer to test yourself; the double-equals is a study-vault convention, not maths notation):

Dennard scaling died around the year 2005, while Moore's law kept doubling transistor counts. The gap between "transistors we own" and "transistors we can power" is called dark silicon.

What broke Dennard scaling?

Voltage stopped scaling below ~0.7 V (threshold voltage

V_{t}

won't drop) and leakage current grew exponentially, so power density no longer stayed constant.

Recall Solution

The three hidden answers are 2005 (Dennard scaling ended), Moore's (law that keeps doubling transistors), and dark silicon (the own-but-cannot-power gap). Dennard scaling (1974–2005) kept power density constant because voltage dropped with each shrink. Once $V$ got stuck near $0.7 V$ , the $V^{2}$ savings stopped, power density climbed, and we could no longer light every transistor. See Dennard-scaling.

Level 2 — Application

Exercise 2.1 (L2)

A $32$ -core chip has $P_{TDP} = 100 W$ and each active core draws $P_{core} = 12.5 W$ . Find (a) active cores, (b) dark silicon fraction.

Recall Solution

(a) $Active = ⌊ \frac{100}{12.5} ⌋ = ⌊ 8 ⌋ = 8$ cores. (b) $D = 1 - \frac{100}{32 \times 12.5} = 1 - \frac{100}{400} = 1 - 0.25 = 0.75 = 75%$ . Answers: 8 active cores, 75% dark. (This is the 2015 / 14 nm row of the generation table reproduced near the top of this page: $N = 32$ , $12.5 W$ /core, $8$ active, $75%$ dark.)

Exercise 2.2 (L2)

A core at $1.0 V$ , $3.0 GHz$ burns $20 W$ of dynamic power. Drop it to $0.8 V$ and $2.0 GHz$ . What is the new dynamic power? (Assume $α, C$ unchanged, so $P \propto V^{2} f$ .)

Recall Solution

This uses dynamic power only, $P_{dynamic} = α C V^{2} f$ from the definition callout. Since $α$ and $C$ are held fixed, they cancel in a ratio, leaving $P \propto V^{2} f$ . Take the ratio of new to old: $P^{'} = P \cdot \frac{V ^{'2}}{V ^{2}} \cdot \frac{f ^{'}}{f} = 20 \cdot \frac{0. 8 ^{2}}{1. 0 ^{2}} \cdot \frac{2.0}{3.0} .$ Step 1 — voltage factor: $0. 8^{2} = 0.64$ (exact). Step 2 — frequency factor: $2.0/3.0 = 0.6 \overline{6}$ (a repeating decimal; we keep $4$ significant figures throughout this page, so $0.6667$ , but carry the exact fraction $\frac{2}{3}$ into the final product to avoid rounding drift). Step 3 — multiply exactly: $20 \times 0.64 \times \frac{2}{3} = \frac{25.6}{3} = 8.5 \overline{3} W$ . Answer: $\approx 8.53 W$ (exactly $\frac{128}{15} W$ ). Notice voltage did the heavy lifting (quadratic) — the DVFS lever.

Exercise 2.3 (L2)

A $64$ -core chip, $P_{TDP} = 100 W$ , each core $2 W$ when active. How many cores can run, and what is the dark fraction?

Recall Solution

$Active = ⌊ 100/2 ⌋ = 50$ cores. $D = \frac{64 - 50}{64} = \frac{14}{64} = 0.21875 = 21.875%$ . Answers: 50 active, $\approx 21.9%$ dark. (This is Option A from Example 1 in the parent.)

Level 3 — Analysis

Exercise 3.1 (L3)

Compare two designs at $100 W$ TDP:

A: $64$ cores, $2 W$ each.
B: $8$ general cores ( $5 W$ each) + $4$ accelerators ( $10 W$ each).

For B, if you run all $8$ general cores plus $2$ accelerators, does it fit in $100 W$ ? What is B's dark silicon fraction over its total potential draw? Also comment on the corner case this exposes.

Recall Solution

Use the generalized formula above, summing over the two unit types. Fit check (this is $P_{used}$ ): $8 (5) + 2 (10) = 40 + 20 = 60 W \leq 100 W$ ✓ (fits with headroom). Total potential draw (everything on) $P_{potential} = \sum_{i} n_{i} P_{i} = 8 (5) + 4 (10) = 40 + 40 = 80 W$ . Dark: $80 - 60 = 20 W$ out of $80 W$ . $D_{B} = 1 - \frac{P _{used}}{P _{potential}} = 1 - \frac{60}{80} = \frac{20}{80} = 0.25 = 25%.$ Answer: fits, $25%$ dark. (The parent's Example 1 lights all accelerators for a $40%$ figure; here we chose to leave 2 accelerators dark — different operating point, same method.) The lesson: dark fraction is an operating choice, not a fixed chip property — see Heterogeneous-computing.

Corner case (important here): design B's total potential draw is only $80 W$ , which is below the $100 W$ TDP. That means chip B could light every unit at once ( $80 W \leq 100 W$ ) and still fit — so its minimum achievable dark fraction is $0%$ with $20 W$ of headroom to spare, exactly the over-budget scenario of Exercise 3.3. The $25%$ figure above is therefore a chosen operating point (2 accelerators deliberately parked), not a power-forced one. When $P_{potential} \leq P_{TDP}$ , dark silicon is entirely optional; contrast design A, whose potential $64 \times 2 = 128 W$ exceeds $100 W$ , forcing at least $⌈(128 - 100) /2 ⌉ = 14$ cores dark no matter what.

Exercise 3.2 (L3)

Consider four generations of a chip family. The budget is fixed at $P_{TDP} = 100 W$ . The core count $N$ quadruples every generation ( $2 \to 8 \to 32 \to 128$ ) while per-core power $P_{core}$ halves every generation ( $50 \to 25 \to 12.5 \to 6.25 W$ ). The figure below plots the resulting dark fraction $D = 1 - \frac{P _{TDP}}{N P _{core}}$ . Explain, using the formula and the plotted points, why $D$ climbs toward $100%$ even though $P_{core}$ is dropping.

Recall Solution

Read the figure first. The horizontal axis is the year (one point per generation); the vertical axis is the dark fraction $D$ in percent. The yellow curve rises $0 \to 50 \to 75 \to 87.5%$ and hugs the pink dashed ceiling at $100%$ without ever crossing it. Each point is labelled with its $N$ and $D$ so you can see the mechanism directly.

Now the formula. Watch the denominator $N \cdot P_{core}$ — the "power needed to light everything":

2005: $2 \times 50 = 100 \Rightarrow D = 1 - 100/100 = 0%$
2010: $8 \times 25 = 200 \Rightarrow D = 1 - 100/200 = 50%$
2015: $32 \times 12.5 = 400 \Rightarrow D = 1 - 100/400 = 75%$
2020: $128 \times 6.25 = 800 \Rightarrow D = 1 - 100/800 = 87.5%$

Each generation $N$ quadruples ( $\times 4$ ) but $P_{core}$ only halves ( $\times \frac{1}{2}$ ), so their product $N P_{core}$ doubles ( $\times 4 \times \frac{1}{2} = \times 2$ ): $100 \to 200 \to 400 \to 800$ . As $N P_{core} \to \infty$ , the fraction $\frac{100}{N P _{core}} \to 0$ , so $D \to 1 = 100%$ — exactly the ceiling the pink dashed line marks. The fixed $100 W$ budget becomes a vanishing slice of an ever-growing pie. The curve approaches but never reaches $100%$ because the budget always lights at least a few cores. See Multi-corescaling.

Exercise 3.3 (L3) — the edge case

What happens to $D$ when the budget is generous — say $P_{TDP} = 300 W$ , $N = 4$ cores, $P_{core} = 50 W$ ? Compute $\frac{P _{TDP}}{N P _{core}}$ and $D$ from the formula. Then interpret: what does a "negative dark fraction" physically mean, and how should we report $D$ ?

Recall Solution

Plug in: $N P_{core} = 4 \times 50 = 200 W$ , but $P_{TDP} = 300 W > 200 W$ . $\frac{P _{TDP}}{N P _{core}} = \frac{300}{200} = 1.5, D = 1 - 1.5 = - 0.5.$ A negative $D$ has no physical meaning — you cannot have " $- 50%$ " of the chip dark. What it really says is: the budget can power every core with $100 W$ to spare, i.e. there is zero dark silicon and excess headroom. How to report it: clamp the fraction to its valid range, $D = max (0, 1 - \frac{P _{TDP}}{N P _{core}}) .$ Whenever $P_{TDP} \geq N P_{core}$ the raw formula gives $\leq 0$ , so report $D = 0%$ (all cores active) and note the leftover budget ( $300 - 200 = 100 W$ ) — spare power for turbo via DVFS or simply cooler, safer operation. Answers: raw $D = - 0.5$ ; reported $D = 0%$ with $100 W$ headroom.

Level 4 — Synthesis

Exercise 4.1 (L4)

A $4$ -core chip: each core at $3.5 GHz$ , $1.0 V$ draws $30 W$ . TDP is $80 W$ . (a) Without DVFS, how many cores run and what is the dark fraction? (b) Apply DVFS to $2.0 GHz$ , $0.8 V$ ( $P \propto V^{2} f$ ). New per-core power? How many cores can now run, and can you light all $4$ ? What is the new dark fraction and total power?

Recall Solution

(a) $Active = ⌊ 80/30 ⌋ = ⌊ 2.67 ⌋ = 2$ cores. Dark $= \frac{4 - 2}{4} = 50%$ . (b) This step scales dynamic power only, $P_{dynamic} = α C V^{2} f$ from the definition callout; with $α, C$ fixed they cancel, giving $P \propto V^{2} f$ . Take the ratio: $P^{'} = 30 \cdot \frac{0. 8 ^{2}}{1. 0 ^{2}} \cdot \frac{2.0}{3.5} = 30 \cdot 0.64 \cdot \frac{2.0}{3.5} = 30 \cdot 0.64 \cdot 0.5714 = 10.97 W .$ (The frequency factor $2.0/3.5 = 0.5714 \dots$ is kept to $4$ significant figures, consistent with Exercise 2.2.) Budget would allow $⌊ 80/10.97 ⌋ = ⌊ 7.29 ⌋ = 7$ cores — but we only own $4$ . So run all $4$ . Total power $= 4 \times 10.97 = 43.9 W \leq 80 W$ ✓. Dark fraction $= 0%$ . Answers: (a) 2 cores, 50% dark. (b) $\approx 10.97 W$ /core, all 4 active, $\approx 43.9 W$ total, $0%$ dark. The trade: slower per-core ( $2.0$ vs $3.5 GHz$ ) but $4$ cores of throughput instead of $2$ .

Exercise 4.2 (L4)

Power-gating turns off idle cores completely, but a gated core still leaks a little. An $8$ -core chip: $P_{TDP} = 80 W$ . If $2$ cores run in Turbo and $6$ are gated, each gated core leaks $P_{static} = 1 W$ . How much power can each turbo core have?

Recall Solution

The $6$ gated cores are not switching, so their dynamic power $α C V^{2} f = 0$ , but their static term $V I_{leak}$ survives — that is the $P_{static} = 1 W$ each still costs. Power stolen by the $6$ leaking dark cores: $6 \times 1 = 6 W$ . Budget left for the $2$ turbo cores: $P_{turbo, total} = P_{TDP} - 6 \cdot P_{static} = 80 - 6 = 74 W$ . Per turbo core: $74/2 = 37 W$ . Answer: $37 W$ per turbo core (matches the parent's Turbo Boost example). This is explicit dark silicon management: redistribute the gone-dark budget into fewer, faster cores.

Level 5 — Mastery

Exercise 5.1 (L5)

A workload is $80%$ parallel, $20%$ serial (Amdahls-law). You have a $16$ -core chip, $P_{TDP} = 100 W$ , each core $12.5 W$ at full speed (giving speed $1.0$ per core). (a) How many cores can run at full speed? What is the maximum speedup by Amdahl's law using that many cores? (b) Now use DVFS to run all $16$ cores at reduced voltage where each draws $6.25 W$ and delivers per-core speed $0.7$ . Compute the new Amdahl speedup with $16$ cores each $0.7 \times$ as fast. Which policy wins?

Amdahl's law: with $n$ parallel workers each of relative speed $r$ , speedup $= \frac{1}{( 1 - p ) + \frac{p}{n r}}$ , where $p$ is the parallel fraction.

Recall Solution

Here $p = 0.80$ , so serial part $1 - p = 0.20$ .

(a) Active cores $= ⌊ 100/12.5 ⌋ = 8$ , each speed $r = 1.0$ . $S_{A} = \frac{1}{0.20 + \frac{0.80}{8 \times 1.0}} = \frac{1}{0.20 + 0.10} = \frac{1}{0.30} = 3.333.$

(b) All $16$ cores fit: $16 \times 6.25 = 100 W = P_{TDP}$ exactly ✓. Each speed $r = 0.7$ . $S_{B} = \frac{1}{0.20 + \frac{0.80}{16 \times 0.7}} = \frac{1}{0.20 + \frac{0.80}{11.2}} = \frac{1}{0.20 + 0.07143} = \frac{1}{0.27143} = 3.684.$

Answers: $S_{A} = 3.33$ , $S_{B} = 3.68$ . The DVFS-everything policy wins ( $3.68 > 3.33$ ) because the extra parallel cores outweigh their slowdown — but only because $p = 0.80$ is high. The serial $0.20$ term dominates the denominator and caps both below $5$ : Amdahl's ceiling ( $1/0.20 = 5$ ) still rules.

Exercise 5.2 (L5)

Same chip and workload as 5.1, but the workload is now only $p = 0.30$ parallel (very serial). Recompute $S_{A}$ (8 full-speed cores, $r = 1.0$ ) and $S_{B}$ (16 cores, $r = 0.7$ ). Which policy wins now, and why does the answer flip?

Recall Solution

$S_{A}$ : $\frac{1}{0.70 + \frac{0.30}{8}} = \frac{1}{0.70 + 0.0375} = \frac{1}{0.7375} = 1.356.$ $S_{B}$ : $\frac{1}{0.70 + \frac{0.30}{16 \times 0.7}} = \frac{1}{0.70 + \frac{0.30}{11.2}} = \frac{1}{0.70 + 0.02679} = \frac{1}{0.72679} = 1.376.$

Answers: $S_{A} = 1.356$ , $S_{B} = 1.376$ . $S_{B}$ still edges ahead, but the gap is razor-thin ( $0.02$ ) versus $0.35$ before. Why it (nearly) flips: when $p$ is small, the serial $1 - p = 0.70$ term swamps the denominator. Adding cores barely helps anyone — extra parallelism has almost nothing to parallelize. Here the tiny per-core slowdown of DVFS ( $0.7 \times$ ) almost cancels its extra-core benefit. Lesson: dark-silicon strategy is workload-dependent — high- $p$ jobs love more slow cores; low- $p$ jobs would rather have a few fast ones (Turbo Boost / Heterogeneous-computing).

Recall Self-test checklist

Active cores formula ::: $⌊ P_{TDP} / P_{core} ⌋$ Dark fraction formula ::: $1 - P_{TDP} / (N P_{core})$ , clamped to $\geq 0$ How does dynamic power scale with voltage and frequency? ::: $V^{2}$ (quadratic) and $f$ (linear), from $P_{dynamic} = α C V^{2} f$ Do gated/dark cores draw power? ::: Yes — static leakage $V I_{leak}$ survives even at $f = 0$ What does a negative raw $D$ mean? ::: Budget exceeds total core draw — no core need be dark, report $D = 0%$ with headroom Amdahl ceiling for parallel fraction $p$ ::: $1/ (1 - p)$