Dark silicon problem: Exercises — Hinglish deep dive

6.4.7 · D4 · Hardware › Power, Thermal & Reliability › Dark silicon problem

Definition Power split ka har symbol — use se pehle define kiya gaya

Ek core do tarike se power consume karta hai (parent note se): $P = dynamic (switching) α C V^{2} f + static (leaking) V I_{leak}$

$α$ = activity factor — un transistors ka fraction jo is cycle mein actually flip ho rahe hain ( $0$ aur $1$ ke beech ek pure number). Zyada flipping = zyada dynamic power.
$C$ = capacitance — kitna charge gates ko har switch pe fill/empty karna padta hai (farads mein measure hota hai). Bade circuits = bada $C$ .
$V$ = supply voltage — electrical "push" (volts). Dynamic power mein yeh squared aata hai, isliye yeh sabse powerful lever hai.
$f$ = clock frequency — har second mein kitne switching cycles hote hain (hertz). Yeh linearly appear karta hai.
$I_{leak}$ = leakage current — current ka wo trickle jo transistor se tab bhi flow karta hai jab wo switch nahi kar raha (amperes). Yahi cheez "dark" silicon ko bhi power waste karwaati hai.

Ratios yaad rakho: dynamic power $V^{2} f$ ke saath scale hoti hai — voltage squared, frequency linear. Neeche har DVFS solution is usi $P_{dynamic} = α C V^{2} f$ line se re-derive hota hai.

Definition Parent ki generation table (yahan reproduce ki gayi hai taaki yeh page akela kaam kare)

Parent note ek chip family ko fixed $P_{TDP} = 100 W$ ke under track karta hai jabki Moore's law transistors double karta rehta hai aur Dennard scaling ruk gayi hai. Yeh page in rows ko refer karta hai, isliye inhe yahan reproduce kiya gaya hai:

Year	Node	Cores $N$	Power/core (W)	Active	Dark
2005	90 nm	2	50	2	0%
2010	45 nm	8	25	4	50%
2015	14 nm	32	12.5	8	75%
2020	7 nm	128	6.25	16	87.5%

Level 1 — Recognition

Exercise 1.1 (L1)

Ek chip mein $N = 16$ cores hain. Uska power budget exactly $4$ cores ko ek saath chalane deta hai. Dark silicon fraction kya hai, percentage mein?

Recall Solution

Dark silicon = wo fraction jo off rehni chahiye = $\frac{16 - 4}{16} = \frac{12}{16} = 0.75 = 75%$ . Answer: $75%$ . Yeh parent note se "16 burners, breaker for 4" wali picture hai.

Exercise 1.2 (L1)

Do power terms mein se — dynamic $α C V^{2} f$ ya static $V I_{leak}$ — kaun sa tab bhi flow karta rehta hai jab ek core switch nahi kar raha (clock effectively idle, $f \to 0$ )?

Recall Solution

$f = 0$ set karo: dynamic power $α C V^{2} f = 0$ . Lekin static power $V I_{leak}$ mein ab bhi transistors pe voltage $V$ hai, isliye current leak hoti rehti hai. Static term survive karta hai. Yahi reason hai ki "dark" silicon bhi power waste karta hai — parent note mein leakage mistake dekho.

Exercise 1.3 (L1)

Blanks bharo aur do historical laws yaad karo (cloze — har ==...== ek answer hide karta hai khud ko test karne ke liye; double-equals study-vault convention hai, maths notation nahi):

Dennard scaling khatam hua 2005 ke aas paas, jabki Moore's law transistor counts double karta raha. "Transistors jo hamare paas hain" aur "transistors jinhe hum power de sakte hain" ke beech ka gap dark silicon kehlata hai.

Dennard scaling kyu toot gayi?

Voltage ~0.7 V se neeche scale karna band ho gaya (threshold voltage

V_{t}

nahi girta) aur leakage current exponentially badhti gayi, isliye power density constant nahi rahi.

Recall Solution

Teen hidden answers hain 2005 (Dennard scaling khatam hua), Moore's (law jo transistors double karta rehta hai), aur dark silicon (own-but-cannot-power gap). Dennard scaling (1974–2005) ne power density ko constant rakha tha kyunki har shrink ke saath voltage girta tha. Jab $V$ ~ $0.7 V$ ke paas atak gaya, $V^{2}$ wali savings ruk gayi, power density badh gayi, aur hum baar har transistor nahi jala sake. Dekho Dennard-scaling.

Level 2 — Application

Exercise 2.1 (L2)

Ek $32$ -core chip ka $P_{TDP} = 100 W$ hai aur har active core $P_{core} = 12.5 W$ draw karta hai. (a) active cores aur (b) dark silicon fraction nikalo.

Recall Solution

(a) $Active = ⌊ \frac{100}{12.5} ⌋ = ⌊ 8 ⌋ = 8$ cores. (b) $D = 1 - \frac{100}{32 \times 12.5} = 1 - \frac{100}{400} = 1 - 0.25 = 0.75 = 75%$ . Answers: 8 active cores, 75% dark. (Yeh page ke top ke paas reproduce ki gayi generation table ki 2015 / 14 nm row hai: $N = 32$ , $12.5 W$ /core, $8$ active, $75%$ dark.)

Exercise 2.2 (L2)

Ek core $1.0 V$ , $3.0 GHz$ pe $20 W$ dynamic power burn karta hai. Ise $0.8 V$ aur $2.0 GHz$ par drop karo. Naya dynamic power kya hoga? (Assume karo $α, C$ unchanged hain, isliye $P \propto V^{2} f$ .)

Recall Solution

Yeh sirf dynamic power use karta hai, $P_{dynamic} = α C V^{2} f$ definition callout se. Kyunki $α$ aur $C$ fixed hain, woh ratio mein cancel ho jaate hain, bass $P \propto V^{2} f$ bachta hai. New se old ka ratio lo: $P^{'} = P \cdot \frac{V ^{'2}}{V ^{2}} \cdot \frac{f ^{'}}{f} = 20 \cdot \frac{0. 8 ^{2}}{1. 0 ^{2}} \cdot \frac{2.0}{3.0} .$ Step 1 — voltage factor: $0. 8^{2} = 0.64$ (exact). Step 2 — frequency factor: $2.0/3.0 = 0.6 \overline{6}$ (repeating decimal; is page mein hum $4$ significant figures rakhte hain, isliye $0.6667$ , lekin rounding drift se bachne ke liye final product mein exact fraction $\frac{2}{3}$ carry karo). Step 3 — exactly multiply karo: $20 \times 0.64 \times \frac{2}{3} = \frac{25.6}{3} = 8.5 \overline{3} W$ . Answer: $\approx 8.53 W$ (exactly $\frac{128}{15} W$ ). Notice karo voltage ne heavy lifting ki (quadratic) — DVFS lever.

Exercise 2.3 (L2)

Ek $64$ -core chip, $P_{TDP} = 100 W$ , har core active hone par $2 W$ . Kitne cores chal sakte hain, aur dark fraction kya hai?

Recall Solution

$Active = ⌊ 100/2 ⌋ = 50$ cores. $D = \frac{64 - 50}{64} = \frac{14}{64} = 0.21875 = 21.875%$ . Answers: 50 active, $\approx 21.9%$ dark. (Yeh parent mein Example 1 se Option A hai.)

Level 3 — Analysis

Exercise 3.1 (L3)

$100 W$ TDP pe do designs compare karo:

A: $64$ cores, $2 W$ each.
B: $8$ general cores ( $5 W$ each) + $4$ accelerators ( $10 W$ each).

B ke liye, agar tum sab $8$ general cores plus $2$ accelerators chalao, toh kya yeh $100 W$ mein fit hoga? B ka dark silicon fraction uske total potential draw par kya hai? Aur uss corner case par bhi comment karo jo yeh expose karta hai.

Recall Solution

Upar di gayi generalized formula use karo, do unit types ke upar sum karte hue. Fit check (yeh $P_{used}$ hai): $8 (5) + 2 (10) = 40 + 20 = 60 W \leq 100 W$ ✓ (headroom ke saath fit hai). Total potential draw (sab on) $P_{potential} = \sum_{i} n_{i} P_{i} = 8 (5) + 4 (10) = 40 + 40 = 80 W$ . Dark: $80 - 60 = 20 W$ out of $80 W$ . $D_{B} = 1 - \frac{P _{used}}{P _{potential}} = 1 - \frac{60}{80} = \frac{20}{80} = 0.25 = 25%.$ Answer: fit hai, $25%$ dark. (Parent ka Example 1 sab accelerators jalata hai aur $40%$ figure aata hai; yahan humne $2$ accelerators dark chodne choose kiye — alag operating point, same method.) Lesson yeh hai: dark fraction ek operating choice hai, chip ki fixed property nahi — dekho Heterogeneous-computing.

Corner case (yahan important): design B ka total potential draw sirf $80 W$ hai, jo $100 W$ TDP se neeche hai. Matlab chip B ek saath har unit jala sakta hai ( $80 W \leq 100 W$ ) aur phir bhi fit rahega — isliye uska minimum achievable dark fraction $0%$ hai aur $20 W$ headroom bacha hai, bilkul Exercise 3.3 wale over-budget scenario ki tarah. Upar wala $25%$ figure isliye ek chosen operating point hai (2 accelerators deliberately parked), power-forced nahi. Jab $P_{potential} \leq P_{TDP}$ ho, dark silicon purely optional hai; design A se compare karo jiska potential $64 \times 2 = 128 W$ $100 W$ se zyada hai, jo kam se kam $⌈(128 - 100) /2 ⌉ = 14$ cores ko dark rehne par majboor karta hai, chahe kuch bhi karo.

Exercise 3.2 (L3)

Ek chip family ki chaar generations consider karo. Budget fixed hai $P_{TDP} = 100 W$ par. Core count $N$ har generation mein chaar guna hota hai ( $2 \to 8 \to 32 \to 128$ ) jabki per-core power $P_{core}$ har generation mein aadha hoti hai ( $50 \to 25 \to 12.5 \to 6.25 W$ ). Neeche ka figure resulting dark fraction $D = 1 - \frac{P _{TDP}}{N P _{core}}$ plot karta hai. Formula aur plotted points use karke explain karo ki $D$ $100%$ ki taraf kyun climb karta hai jabki $P_{core}$ gir raha hai.

Recall Solution

Pehle figure padho. Horizontal axis year hai (har generation ka ek point); vertical axis dark fraction $D$ percent mein hai. Yellow curve $0 \to 50 \to 75 \to 87.5%$ se utha hai aur pink dashed ceiling at $100%$ ke paas rehta hai bina cross kiye. Har point pe $N$ aur $D$ labeled hai taaki tum mechanism seedha dekh sako.

Ab formula. Denominator $N \cdot P_{core}$ dekho — "sab kuch jalane ke liye zaroori power":

2005: $2 \times 50 = 100 \Rightarrow D = 1 - 100/100 = 0%$
2010: $8 \times 25 = 200 \Rightarrow D = 1 - 100/200 = 50%$
2015: $32 \times 12.5 = 400 \Rightarrow D = 1 - 100/400 = 75%$
2020: $128 \times 6.25 = 800 \Rightarrow D = 1 - 100/800 = 87.5%$

Har generation mein $N$ chaar guna ( $\times 4$ ) hota hai lekin $P_{core}$ sirf aadha ( $\times \frac{1}{2}$ ) hota hai, isliye unka product $N P_{core}$ double hota hai ( $\times 4 \times \frac{1}{2} = \times 2$ ): $100 \to 200 \to 400 \to 800$ . Jab $N P_{core} \to \infty$ , fraction $\frac{100}{N P _{core}} \to 0$ , isliye $D \to 1 = 100%$ — exactly woh ceiling jo pink dashed line mark karti hai. Fixed $100 W$ budget ek kabhi badhte pie ka ek shrinking slice ban jaata hai. Curve $100%$ ke paas jaata hai lekin kabhi reach nahi karta kyunki budget hamesha kam se kam kuch cores jalata hai. Dekho Multi-corescaling.

Exercise 3.3 (L3) — edge case

Kya hota hai jab budget generous ho — maano $P_{TDP} = 300 W$ , $N = 4$ cores, $P_{core} = 50 W$ ? Formula se $\frac{P _{TDP}}{N P _{core}}$ aur $D$ compute karo. Phir interpret karo: "negative dark fraction" physically kya matlab hai, aur $D$ ko kaise report karna chahiye?

Recall Solution

Plug in karo: $N P_{core} = 4 \times 50 = 200 W$ , lekin $P_{TDP} = 300 W > 200 W$ . $\frac{P _{TDP}}{N P _{core}} = \frac{300}{200} = 1.5, D = 1 - 1.5 = - 0.5.$ Negative $D$ ka koi physical matlab nahi — tumhare paas " $- 50%$ " chip dark nahi ho sakti. Yeh actually keh raha hai: budget har core power kar sakta hai aur $100 W$ bachi rahegi, matlab zero dark silicon hai aur excess headroom hai. Ise kaise report karein: fraction ko uske valid range mein clamp karo, $D = max (0, 1 - \frac{P _{TDP}}{N P _{core}}) .$ Jab bhi $P_{TDP} \geq N P_{core}$ ho, raw formula $\leq 0$ deta hai, isliye $D = 0%$ report karo (sab cores active) aur leftover budget ( $300 - 200 = 100 W$ ) note karo — spare power turbo ke liye DVFS via, ya bas thanda, safe operation ke liye. Answers: raw $D = - 0.5$ ; reported $D = 0%$ with $100 W$ headroom.

Common mistake L3 trap: dark fraction ko chip ki intrinsic constant maanna — aur use negative jaane dena

Kyun sahi lagta hai: "Ek chip ka dark silicon percentage hai" sunne mein ek spec jaisa lagta hai, jaise clock speed. Aur formula kisi bhi input ke liye number deta rehta hai. Fix: $D$ depend karta hai tum chip ko kaise operate karte ho — kaun se cores, kaun sa voltage, kaun se accelerators (Exercise 3.1). Aur $D$ sirf $[0, 1)$ mein meaningful hai: agar $P_{TDP} \geq N P_{core}$ ho toh raw value $\leq 0$ ho jaati hai, jiiska matlab sirf yeh hai ki koi core dark nahi hona chahiye — $0%$ par clamp karo (Exercise 3.3). Kam voltage (DVFS) ya halke cores $P_{core}$ badal dete hain aur instantly $D$ badal jaata hai; same silicon $50%$ dark, $0%$ dark, ya excess budget wala ho sakta hai tumhari policy ke hisaab se.

Level 4 — Synthesis

Exercise 4.1 (L4)

Ek $4$ -core chip: har core $3.5 GHz$ , $1.0 V$ pe $30 W$ draw karta hai. TDP $80 W$ hai. (a) DVFS ke bina, kitne cores chalenge aur dark fraction kya hoga? (b) DVFS apply karo $2.0 GHz$ , $0.8 V$ tak ( $P \propto V^{2} f$ ). Naya per-core power kya hoga? Kitne cores ab chal sakte hain, aur kya tum sab $4$ jala sakte ho? Naya dark fraction aur total power kya hai?

Recall Solution

(a) $Active = ⌊ 80/30 ⌋ = ⌊ 2.67 ⌋ = 2$ cores. Dark $= \frac{4 - 2}{4} = 50%$ . (b) Yeh step sirf dynamic power scale karta hai, $P_{dynamic} = α C V^{2} f$ definition callout se; $α, C$ fixed hone se woh cancel hote hain, giving $P \propto V^{2} f$ . Ratio lo: $P^{'} = 30 \cdot \frac{0. 8 ^{2}}{1. 0 ^{2}} \cdot \frac{2.0}{3.5} = 30 \cdot 0.64 \cdot \frac{2.0}{3.5} = 30 \cdot 0.64 \cdot 0.5714 = 10.97 W .$ (Frequency factor $2.0/3.5 = 0.5714 \dots$ ko $4$ significant figures tak rakha gaya hai, Exercise 2.2 ke consistent.) Budget $⌊ 80/10.97 ⌋ = ⌊ 7.29 ⌋ = 7$ cores allow karega — lekin hamare paas sirf $4$ hain. Isliye sab $4$ chalao. Total power $= 4 \times 10.97 = 43.9 W \leq 80 W$ ✓. Dark fraction $= 0%$ . Answers: (a) 2 cores, 50% dark. (b) $\approx 10.97 W$ /core, sab 4 active, $\approx 43.9 W$ total, $0%$ dark. Trade-off: per-core slower ( $2.0$ vs $3.5 GHz$ ) lekin $2$ ki jagah $4$ cores ka throughput milta hai.

Exercise 4.2 (L4)

Power-gating idle cores ko completely off karta hai, lekin ek gated core thoda leak karta rehta hai. Ek $8$ -core chip: $P_{TDP} = 80 W$ . Agar $2$ cores Turbo mein chalen aur $6$ gated hon, aur har gated core $P_{static} = 1 W$ leak kare, toh har turbo core ko kitni power mil sakti hai?

Recall Solution

$6$ gated cores switch nahi kar rahe, isliye unka dynamic power $α C V^{2} f = 0$ , lekin unka static term $V I_{leak}$ survive karta hai — yahi $P_{static} = 1 W$ hai jo har ek ab bhi cost karta hai. $6$ leaking dark cores ki chori gayi power: $6 \times 1 = 6 W$ . $2$ turbo cores ke liye bacha hua budget: $P_{turbo, total} = P_{TDP} - 6 \cdot P_{static} = 80 - 6 = 74 W$ . Per turbo core: $74/2 = 37 W$ . Answer: $37 W$ per turbo core (parent ke Turbo Boost example se match karta hai). Yeh explicit dark silicon management hai: gone-dark budget ko fewer, faster cores mein redistribute karo.

Level 5 — Mastery

Exercise 5.1 (L5)

Ek workload $80%$ parallel aur $20%$ serial hai (Amdahls-law). Tumhare paas ek $16$ -core chip hai, $P_{TDP} = 100 W$ , har core $12.5 W$ full speed par (speed $1.0$ per core deta hai). (a) Full speed par kitne cores chal sakte hain? Utne cores use karke Amdahl's law se maximum speedup kya hai? (b) Ab DVFS use karo sab $16$ cores ko reduced voltage par chalane ke liye jahan har ek $6.25 W$ draw kare aur per-core speed $0.7$ de. $16$ cores ke saath naya Amdahl speedup compute karo jab har ek $0.7 \times$ as fast ho. Kaun si policy jeet'ti hai?

Amdahl's law: $n$ parallel workers ke saath har ek relative speed $r$ par, speedup $= \frac{1}{( 1 - p ) + \frac{p}{n r}}$ , jahan $p$ parallel fraction hai.

Recall Solution

Yahan $p = 0.80$ , isliye serial part $1 - p = 0.20$ .

(a) Active cores $= ⌊ 100/12.5 ⌋ = 8$ , har ek speed $r = 1.0$ . $S_{A} = \frac{1}{0.20 + \frac{0.80}{8 \times 1.0}} = \frac{1}{0.20 + 0.10} = \frac{1}{0.30} = 3.333.$

(b) Sab $16$ cores fit hote hain: $16 \times 6.25 = 100 W = P_{TDP}$ exactly ✓. Har ek speed $r = 0.7$ . $S_{B} = \frac{1}{0.20 + \frac{0.80}{16 \times 0.7}} = \frac{1}{0.20 + \frac{0.80}{11.2}} = \frac{1}{0.20 + 0.07143} = \frac{1}{0.27143} = 3.684.$

Answers: $S_{A} = 3.33$ , $S_{B} = 3.68$ . DVFS-everything policy jeet'ti hai ( $3.68 > 3.33$ ) kyunki extra parallel cores unke slowdown se zyada faida dete hain — lekin sirf isliye kyunki $p = 0.80$ high hai. Serial $0.20$ term denominator ko dominate karta hai aur dono ko $5$ se neeche cap karta hai: Amdahl's ceiling ( $1/0.20 = 5$ ) tab bhi rule karta hai.

Exercise 5.2 (L5)

Same chip aur workload jaise 5.1 mein, lekin ab workload sirf $p = 0.30$ parallel hai (bahut serial). $S_{A}$ (8 full-speed cores, $r = 1.0$ ) aur $S_{B}$ (16 cores, $r = 0.7$ ) recompute karo. Ab kaun si policy jeet'ti hai, aur answer kyun palatta hai?

Recall Solution

$S_{A}$ : $\frac{1}{0.70 + \frac{0.30}{8}} = \frac{1}{0.70 + 0.0375} = \frac{1}{0.7375} = 1.356.$ $S_{B}$ : $\frac{1}{0.70 + \frac{0.30}{16 \times 0.7}} = \frac{1}{0.70 + \frac{0.30}{11.2}} = \frac{1}{0.70 + 0.02679} = \frac{1}{0.72679} = 1.376.$

Answers: $S_{A} = 1.356$ , $S_{B} = 1.376$ . $S_{B}$ ab bhi thoda aage hai, lekin gap bahut thin hai ( $0.02$ ) pehle ke $0.35$ ke muqable. Kyun (almost) palattha hai: jab $p$ chhota ho, serial term $1 - p = 0.70$ denominator ko swamp kar deta hai. Cores add karna kisi ko bhi zyada help nahi karta — extra parallelism ke paas parallelize karne ke liye almost kuch nahi hai. Yahan DVFS ka chhota per-core slowdown ( $0.7 \times$ ) uske extra-core benefit ko almost cancel kar deta hai. Lesson: dark-silicon strategy workload-dependent hai — high- $p$ jobs zyada slow cores chahte hain; low- $p$ jobs kuch fast cores prefer karenge (Turbo Boost / Heterogeneous-computing).

Recall Self-test checklist

Active cores formula ::: $⌊ P_{TDP} / P_{core} ⌋$ Dark fraction formula ::: $1 - P_{TDP} / (N P_{core})$ , $\geq 0$ par clamped Dynamic power voltage aur frequency ke saath kaise scale hoti hai? ::: $V^{2}$ (quadratic) aur $f$ (linear), $P_{dynamic} = α C V^{2} f$ se Kya gated/dark cores power draw karte hain? ::: Haan — static leakage $V I_{leak}$ $f = 0$ par bhi survive karta hai Negative raw $D$ ka kya matlab hai? ::: Budget total core draw se zyada hai — koi core dark nahi hona chahiye, $D = 0%$ with headroom report karo Parallel fraction $p$ ke liye Amdahl ceiling ::: $1/ (1 - p)$