Dark silicon problem: Question bank — Hinglish deep dive

6.4.7 · D5 · Hardware › Power, Thermal & Reliability › Dark silicon problem

Shuru karne se pehle, neeche use hone wala har symbol apna meaning earn karta hai taaki kuch bhi mystery na rahe.

Definition Is page par har symbol, words mein

$α$ — activity factor: un transistors ka fraction jo har clock tick mein actually 0↔1 flip kar rahe hain. $α = 1$ matlab sab switch karte hain; $α = 0$ matlab koi nahi karta.
$C$ — capacitance jo tab charge aur discharge hoti hai jab transistors switch karte hain; ise ek chhoti "bucket" of charge ki size ki tarah socho jo har gate ko fill karni padti hai.
$V$ — supply voltage jo transistors ko feed karta hai.
$f$ — clock frequency (switches per second).
$I_{leak}$ — upar bataya gaya leakage current per transistor.
$P_{dynamic}$ — dynamic power: watts jo transistors ke actively switch karne se burn hoti hain, neeche $α C V^{2} f$ se di gayi hai.
$P_{static}$ — static (leakage) power: watts jo tab bhi burn hoti hain jab kuch switch nahi karta, involved transistors par $V I_{leak}$ ke sum ke barabar.
$N$ — chip par physically total cores ki sankhya.
$P_{core}$ — wo power jo ek core active hone par draw karta hai (neeche diye symbols se bana).
$⌊ \cdot ⌋$ — floor function: nearest whole number tak neeche round karo, kyunki tum fractional core nahi chala sakte.

Related builds in hain Dennard-scaling, Mores-law, TDP-and-power-budget, DVFS, Power-gating, Heterogeneous-computing, Amdahls-law aur Multi-corescaling.

Figure padhna: horizontal axis process generation hai (2005→2020); vertical axis cores ki sankhya hai log-base-2 scale par (har gridline ek doubling hai). Cyan bars woh total cores dikhate hain jo transistor budget provide karta hai (Moore's Law — 2, 8, 32, 128). Chhote amber bars, aage drawn, dikhate hain ki un cores mein se kitne fixed TDP actually power kar sakta hai (2, 4, 8, 16). Cyan-minus-amber gap, "dark" label kiya hua, dark silicon hai: 2005 mein 0 cores se 2020 tak 112 cores tak badh raha hai. Same watts, ever more idle transistors.

True ya false — justify karo

Dark silicon ka matlab hai wo transistors toot gaye hain ya defective hain.

False. Woh poori tarah functional hain; unhe simply ek saath on allowed nahi hai kyunki shared power/heat budget unhe sab ko feed nahi kar sakta — jaise 16 burners hona lekin ek breaker jo 4 se zyada par trip kar jaaye.

Agar Dennard scaling kabhi break nahi hua hota, tab bhi dark silicon problem hoti.

False. Working Dennard scaling ke under, power-per-core bilkul utni hi tezi se shrink hoti hai jitni core count badhti hai, toh total power flat rehti hai aur har core on reh sakta hai. Dark silicon Dennard ke breakdown ka ek symptom hai.

Moore's Law ke marne se dark silicon hua.

False — yeh ulta hai. Mores-law abhi bhi (mostly) alive hai: hume zyada transistors milte rehte hain. Dark silicon isliye exist karta hai kyunki Moore jeeta hai lekin Dennard-scaling mar gaya — hume transistors milte hain lekin unhe power nahi kar sakte.

0% dark silicon wala chip hamesha best-designed chip hota hai.

False. 0% dark ka matlab sirf yeh hai ki har transistor TDP ke under fit hota hai, aksar isliye kyunki few cores hain ya slow chalte hain. Zyada dark fraction lekin powerful accelerators wala chip real workloads par use crush kar sakta hai — jaise few general cores plus accelerators ka heterogeneous mix zyada dark fraction dikhaa sakta hai phir bhi target workloads (video, ML) par Heterogeneous-computing ke zariye jeet sakta hai.

Dark silicon koi power consume nahi karta kyunki yeh switched off hai.

False. "Off" yahaan usually matlab hai "switching nahi kar raha," toh

P_{dynamic} = 0

, lekin transistors abhi bhi

P_{static} = V I_{leak}

leak karte hain. Sirf true Power-gating (voltage supply kaatna) leakage remove karta hai, aur woh bhi imperfect hai.

Voltage utni hi fraction se girane par frequency girane se zyada power bachti hai.

True. Dynamic power hai

P_{dynamic} = α C V^{2} f

V

aadha karo:

V^{2}

term

\frac{1}{4}

ho jaati hai, toh power quarter ho jaati hai. Iske bajaay

f

aadha karo: power sirf half hoti hai. Toh 20% voltage cut ~36% (

1 - 0. 8^{2}

) bachata hai jabki 20% frequency cut sirf 20% bachata hai.

Turbo Boost TDP ceiling violate karta hai aur faster jaata hai.

False. Turbo TDP ke under rehta hai. Yeh zyada tar cores park kar deta hai (unka budget free karta hai) aur woh freed power 1–2 active cores ko de deta hai, toh single-thread speed ceiling toode bina badhti hai.

Har generation cores ki sankhya double karna performance double karta hai.

False. Performance

\propto

active cores

= ⌊ P_{TDP} / P_{core} ⌋

. Agar

P_{core}

shrink karna band ho jaaye (Dennard ka end), toh active cores flat rehte hain chahe total cores

N

double ho jaayein — tum dark silicon gain karte ho, speed nahi.

Static (leakage) power chhote nodes par worse ho gayi.

True. Jaise oxide layers patli huin, electrons unke through quantum-tunnel karne lage, toh

I_{leak}

sharply badhi aur iske saath

P_{static} = V I_{leak}

bhi. 7nm/5nm par, leakage total power ka 30–50% ho sakti hai.

Supply voltage hamesha ke liye neeche scale karta reh sakta hai power bachane ke liye.

False. Roughly

0.7 V

ke neeche supply voltage

V

transistor ki threshold voltage

V_{t}

ke paas aa jaata hai, aur switching slow aur unreliable ho jaati hai. Yeh voltage floor ek core reason hai kyun Dennard scaling ruk gayi.

Error dhundho

"Hamare paas 128 cores hain aur 100W TDP hai 6.25W per core ke saath, toh sab 128 ek saath chalte hain."

Error: active cores

= ⌊ 100/6.25 ⌋ = 16

, 128 nahi. Baaki 112 dark rehne chahiye — woh

87.5%

dark silicon hai.

"Power density

= α C V^{2} f / A

(per unit area

A

); jab transistors shrink hote hain, density badhti hai, toh scaling hamesha chips ko garam karti hai."

Error: ideal Dennard scaling ke under factors cancel ho jaate hain. Maano ek generation linear size ko

s > 1

se shrink kare, toh

C \to C / s

V \to V / s

(isliye

V^{2} \to V^{2} / s^{2}

), aur area

A \to A / s^{2}

. Frequency

s f

tak badhti hai kyunki ek chhota transistor

1/ s

time mein switch karta hai — ek gate jo

s

times faster flip kare woh

s

times clock par chalta hai. Tab

\frac{α ( C / s ) ( V ^{2} / s ^{2} ) ( s f )}{A / s ^{2}} = \frac{α C V ^{2} f}{A}

— density constant hai. Yeh sirf isliye badhi kyunki

V

stuck ho gaya (

s

se nahi drop kar saka) jabki

f

badhta raha — ek breakdown hai, rule nahi.

"DVFS tumhe 4-core chip par 7 cores chalane deta hai kyunki

⌊ 80/11 ⌋ = 7

Error: formula ek ceiling of 7 deta hai, lekin tum physically jo

N = 4

cores hain unse zyada nahi chala sakte. Real result hai saare 4 cores active (

4 \times 11 = 44

< 80

W TDP), yaani 0% dark.

"Accelerators wasteful hain — woh zyada tar time dark baithe rehte hain."

Error framing: dark baithna theek hai kyunki jab gated hote hain toh unki leakage

P_{static}

choti hoti hai. Active hone par woh 10–100× better performance-per-watt deliver karte hain, jo precisely woh tarika hai jisse Heterogeneous-computing ek fixed budget achhe se kharach karta hai.

"Kyunki dark regions off hain, thermal model mein unhe ignore kar sakte hain."

Error: dark transistors abhi bhi har ek

P_{static} = V I_{leak}

jalate hain, toh unka ek region real heat add karta hai. Is static power ko ignore karna temperature underestimate karta hai aur thermal throttling trip kar sakta hai.

"Power gating free hai — sirf supply kato aur turant wake it back up karo."

Error: Power-gating

P_{static}

ko zero karta hai, lekin region ko wapas wake karne par uski capacitance

C

recharge hoti hai aur roughly

1 0^{2}

nanoseconds se milliseconds tak ka time lagta hai — yeh ek measurable latency aur energy cost hai, zero nahi.

Why questions

Ek fixed TDP, transistor count nahi, decide karta hai ki kitne cores chal sakte hain — kyun?

Kyunki heat removal sachcha bottleneck hai:

P_{TDP}

woh wattage hai jo cooler carry away kar sakta hai. Transistors saste aur plentiful hain; sustained heat ke watts scarce, capped resource hain.

Specialization (Heterogeneous-computing, accelerators) dark silicon ke against kyun help karta hai, sirf zyada general cores add karne ke bajaay?

Ek general core bohot saare watts kharach karta hai woh kaam karne ke liye jo ek accelerator fraction of energy mein karta hai. Zyada work per watt milne ka matlab hai ki fixed budget ka zyada hissa useful results mein convert hota hai, chahe accelerator idle hone par dark ho.

Amdahls-law Dennard era se zyada ab kyun matter karta hai?

Jab tum free mein sirf active cores add nahi kar sakte, toh remaining speedups software parallelism se aane chahiye — aur Amdahl's Law cap karta hai ki serial fraction kitna benefit le sakta hai, isliye algorithmic efficiency nayi frontier ban gayi hai.

DVFS pehle voltage scaling ka lever kyun pakadta hai?

Kyunki

P_{dynamic}

V^{2}

par depend karta hai: ek chhota voltage drop ek bada, quadratic power saving deta hai, jisse zyada cores TDP ke under fit ho sakte hain. Frequency

f

saath mein reduce ki jaati hai kyunki kam voltage zyada frequency sustain nahi kar sakta.

Turbo Boost ek single app par laptop fast feel karata hai lekin heavy multithreaded par nahi — kyun?

Turbo single-thread bursts ke liye poora freed budget 1–2 cores mein concentrate karta hai. Jab sab cores loaded hain, redistribute karne ke liye koi idle budget nahi hota, toh har core base clock ke paas rehta hai.

Dark silicon fraction har generation 100% ki taraf kyun creep karta hai?

Core count

N

double hota hai (Moore) jabki

P_{TDP}

cooling limits se flat rakhaa jaata hai aur

P_{core}

barely drop karta hai (Dennard broken). Toh ratio

P_{TDP} / (N \cdot P_{core}

) har node par shrink hota hai, aur dark fraction

= 1 -

woh ratio badhta hai.

Edge cases

Ek single-core chip jiska ek core TDP se kam draw karta hai — uska dark silicon fraction kya hai?

0%.

N = 1

aur

P_{core} \leq P_{TDP}

ke saath, ratio

P_{TDP} / (N P_{core}) \geq 1

, toh kuch bhi dark nahi rehna chahiye (fraction 0 par clamp hai, kabhi negative nahi).

Dark fraction formula negative number deta hai — iska kya matlab hai?

Matlab yeh hai ki

P_{TDP}

total possible core draw

N \cdot P_{core}

se exceed karta hai, toh sab cores fit ho jaate hain aur spare budget bhi hai. Ek negative result physically 0% dark pada jaata hai (aur possibly DVFS ya turbo ke liye headroom hai).

Ek single core jiska power draw poore TDP se exceed karta hai — kya hota hai?

⌊ P_{TDP} / P_{core} ⌋ = 0

: zero cores us voltage/frequency par chal sakte hain, toh chip effectively 100% dark hai. Iska sirf ek hi escape hai DVFS —

V

aur

f

drop karo jab tak ek core ki power TDP ke under na aa jaaye.

Agar tum TDP badhaao (bada heatsink, liquid cooling) toh dark silicon ka kya hota hai?

Zyada budget matlab zyada active cores, toh dark fraction kam hota hai. Lekin TDP bina limit ke nahi badh sakta — heat removal aur hot-spot temperature eventually ise cap kar dete hain, isliye cooling akela dark silicon cancel nahi kar sakta.

Ek chip jahan har core power-gated off hai — kya koi power consume hoti hai?

Almost zero, kyunki gating

P_{static} \to 0

drive karta hai aur

P_{dynamic} = 0

. Lekin kuch always-on control logic ek chhota residual draw rakhti hai, toh "fully off" ek approximation hai, true zero nahi.

Exactly TDP boundary par jahan

P_{TDP}

P_{core}

ka integer multiple hai, wahan kitne cores chalte hain?

Exactly

P_{TDP} / P_{core}

cores, kyunki ek integer ka floor woh khud hota hai — last core zero headroom ke saath just fit ho jaata hai, turbo ya variation ke liye koi slack nahi.

Agar per-core power har generation half ho jaaye (Dennard restored), toh cores double hone par dark silicon ka kya hota hai?

Woh apne current level par flat rehta hai.

N

double karna aur

P_{core}

half karna

N \cdot P_{core}

constant rakhta hai, toh same TDP same fraction power karta hai — wahi balance jo early chips ko 0% dark rakhta tha.

Recall Fast self-test

Dark silicon exist karta hai kyunki Moore ___ aur Dennard ___. ::: jeeta hai (zyada transistors) / mar gaya (unhe sab ko power nahi kar sakte). Woh lever jo DVFS pehle pakadta hai, aur kyun. ::: Voltage $V$ , kyunki $P_{dynamic}$ $V^{2}$ se scale karta hai (quadratic saving). Reason kyun "off" cores abhi bhi power cost karte hain. ::: Leakage $P_{static} = V I_{leak}$ tab tak flow karti rehti hai jab tak true power-gating supply nahi kaat deta.