Dark silicon problem — Hinglish notes

6.4.7 · Hardware › Power, Thermal & Reliability

The Physics Behind Dark Silicon

Power Density Crisis

The fundamental equations:

$P_{dynamic} = α C V^{2} f$

$P_{static} = V I_{leak}$

Jahaan:

$α$ = activity factor (transistors switching ka fraction)
$C$ = capacitance
$V$ = supply voltage
$f$ = clock frequency
$I_{leak}$ = leakage current

Dennard scaling kyun toot gayi:

Lekin reality 65nm ke around alag ho gayi:

Voltage $\sim$ 0.7V se neeche scale nahi ho sakta → transistors reliably switch karna band kar dete hain (threshold voltage $V_{t}$ proportionally scale nahi hoti)
Leakage explode karti hai → $I_{leak}$ exponentially badhti hai jab oxide thickness shrink hoti hai (quantum tunneling)
Power density badhti hai → $P \propto f$ lekin $V$ stuck hai, toh $P$ frequency ke saath badhti hai

Quantifying Dark Silicon

Example evolution (Moore's Law jaari hai, Dennard scaling ruk gayi):

| Year | Node | Cores | TDP (W) | Power/core (W) | Active | Dark % | |------|------|---------|-------------|--------|--------| | 2005 | 90nm | 2 | 100 | 50 | 2 | 0% | | 2010 | 45nm | 8 | 100 | 25 | 4 | 50% | | 2015 | 14nm | 32 | 100 | 12.5 | 8 | 75% | | 2020 | 7nm | 128 | 100 | 6.25 | 16 | 87.5% |

Yeh kyun matter karta hai: Har process generation mein, hum transistor count double karte hain lekin TDP fixed rehta hai (cooling limits). Dark silicon fraction 100% ke paas pahunchti jaati hai.

Consequences and Trade-offs

Worked example Example 1: Many-Core vs. Accelerator Strategy

Scenario: 100W TDP chip, 16nm node. Aap ya toh fit kar sakte ho:

Option A: 64 simple cores, active hone par 2W each
Option B: 8 general cores (5W each) + 4 specialized accelerators (10W each)

Analysis Option A:

Active cores: $⌊ 100/2 ⌋ = 50$ cores max
Dark silicon: $(64 - 50) /64 = 21.9%$
Achha hai: highly parallel workloads ke liye

Analysis Option B:

Saare 8 cores + 2 accelerators = $8 (5) + 2 (10) = 60$ W → fit ho jaata hai!
Dark silicon: $(4 (10) + 8 (5) - 60) / (4 (10) + 8 (5)) = 40/100 = 40%$
Achha hai: specialized workloads ke liye (video, crypto, ML)

Yeh step kyun? Option B mein dark silicon ka percentage zyada hai lekin target workloads par potentially better performance hai—yahi key insight hai jo heterogeneous architectures ko drive karti hai.

Worked example Example 2: Dynamic Voltage-Frequency Scaling (DVFS)

Problem: Ek 4-core chip chalao jahaan har core max frequency (3.5 GHz, 1.0V) par 30W consume karta hai, lekin TDP 80W hai.

DVFS ke bina:

Chal sakta hai: $⌊ 80/30 ⌋ = 2$ cores
Dark: 2 cores (50%) DVFS ke saath (2.0 GHz, 0.8V par reduce karo):
Power scales karta hai: $P \propto V^{2} f$ → $P^{'} = 30 \cdot (0. 8^{2}) \cdot (2.0/3.5) = 30 \cdot 0.64 \cdot 0.571 \approx 11$ W
Chal sakta hai: $⌊ 80/11 ⌋ = 7$ cores… ruko, hamare paas sirf 4 hain!
Saare 4 cores active total 44W par, 0% dark silicon Trade-off: Lower per-core performance (2.0 vs 3.5 GHz) lekin higher throughput (4 cores vs 2).

Yeh step kyun? Voltage scaling quadratic hai, toh 1.0V se 0.8V par jaane se power 36% cut ho jaati hai. Frequency scaling linear hai. Dono mil ke lower performance par full utilization enable karte hain.

Architectural Responses

Industry ne teen main strategies adopt ki hain:

Heterogeneous architectures (big.LITTLE, ARM DynamIQ)
- High-performance aur power-efficient cores ka mix
- Tasks ko appropriate core types par schedule karo
- Example: Apple M-series (performance + efficiency cores)
Specialized accelerators (GPU, TPU, neural engines)
- Specific domains ke liye fixed-function units
- General cores se 10-100× better performance-per-watt
- Use na hone par dark silicon, lekin active hone par massive wins
Dynamic resource management
- DVFS: voltage/frequency ko per-core adjust karo
- Power gating: unused regions ko completely shut off karo
- Thread migration aur load balancing

Common mistake Common Misconception: "Bas Aur Cores Add Karo"

Galat reasoning: Moore's Law abhi bhi kaam kar raha hai, toh har 2 saal mein cores double karne se performance double ho jaayegi.

Yeh sahi kyun lagta hai: Historically (1990s-2005), zyada transistors = zyada performance. Hum is scaling ki expect karne ke aadi ho gaye hain.

Reality yeh hai: $Performance \propto Active cores = \frac{P _{TDP}}{P _{core}}$

Agar $P_{TDP}$ fixed hai aur $P_{core}$ scale down nahi hoti (Dennard breakdown), toh active cores constant rehte hain chahe total core count badhta rahe. Tumhe milta hai:

Zyada transistors (Moore's Law ✓)
Same active cores (Dark silicon ✗)
Extra cores se performance gain nahi

Fix: Performance growth ab require karti hai:

Better algorithms/software (Amdahl's Law aur zyada matter karta hai)
Heterogeneous designs (sahi task ke liye sahi core)
Specialization (common operations ke liye accelerators)
Reduced voltage operation (efficiency ke liye frequency sacrifice karo)

Connections to Other Topics

Dennard-scaling — woh breakdown jo dark silicon cause karta hai
Mores-law — woh transistors provide karta hai jo hum fully utilize nahi kar sakte
TDP-and-power-budget — woh constraint jo darkness create karta hai
Amdahls-law — software parallelism ko limit karta hai, dark silicon ko aur worse banata hai
Heterogeneous-computing — dark silicon ka architectural response
DVFS — dark silicon ko dynamically manage karne ki technique
Power-gating — dark regions mein leakage reduce karne ka method
Multi-corescaling — kyun cores add karne ke diminishing returns hain

Recall Ek 12-Saal-Ke Bachche Ko Samjhao

Tumhe pata hai jab tumhe ek bada crayon box milta hai, jaise 64-pack? Tumhare paas bahut saare colors hote hain, lekin agar tum unhe sab ek saath use karne ki koshish karo, toh itni tezi se coloring karne se tumhara haath thak jaata hai aur garam ho jaata hai, hai na?

Computer chips bhi aise hi hoti hain! Engineers aisi chips bana sakte hain jinmein hundreds of "cores" hon (jaise andar chhote-chhote computers). Lekin yahan ek catch hai: agar tum unhe sab ek saath full speed par run karne ki koshish karo, toh chip BAHUT zyada garam ho jaati hai—itni garam ki woh khud ko break kar le!

Toh chahe tumhare paas 100 cores hain, tum ek waqt mein shayad sirf 25 ko on kar sako. Baaki 75 ko wahan bekar baithna padta hai, "dark" rehte hain aur off rehte hain. Yahi dark silicon hai—yeh aise hai jaise tumhare paas woh crayons hain jinke paise tumne diye lekin use nahi kar sakte kyunki tumhara haath aag pakad leta.

Yeh kyun hota hai? Purane computers zyada powerful ban sakte the cheezein chhoti banakar AUR kam electricity use karke. Lekin lagbhag 20 saal pehle, "kam electricity use karna" wala part kaam karna band ho gaya. Ab hum cheezein chhoti bana sakte hain (box mein zyada crayons!), lekin har crayon abhi bhi same electricity use karta hai. Toh hum crayons use karne se pehle hi power budget khatam kar lete hain.

Active Recall Flashcards

#flashcards/hardware

What is dark silicon? :: Ek chip ke transistors ka woh fraction jo kisi bhi waqt power aur thermal constraints ki wajah se powered off rehna padta hai, jabki woh physically present aur functional hote hain.

Why did dark silicon emerge as a problem?

Dennard scaling breakdown ho gayi (~2005) isliye power density transistors shrink hone ke saath constant nahi rehti. Voltage ~0.7V se neeche scale nahi ho sakta aur leakage current explode ho gayi, matlab TDP fixed raha jabki transistor count badhta raha (Moore's Law).

What is the formula for dark silicon fraction?

Dark fraction = 1 - (P_TDP)/(N × P_core), jahaan N total cores hain, P_TDP thermal design power hai, aur P_core power per core hai jab active ho.

How does dynamic power scale with voltage and frequency?

P_dynamic = α C V² f, jahaan voltage dependence quadratic (V²) hai aur frequency dependence linear (f) hai.

Why did Dennard scaling predict constant power density?

Jab dimensions factor s se shrink hue, capacitance aur voltage dono s se drop hue (voltage squared s² se), frequency s se badhi, aur area s² se drop hui. Factors cancel ho gaye: P/A constant rahi.

What are three main architectural responses to dark silicon?

1) Heterogeneous architectures (big.LITTLE cores), 2) Specialized accelerators (GPUs, TPUs), 3) Dynamic resource management (DVFS, power gating).

How does Turbo Boost relate to dark silicon?

Turbo Boost deliberately dark silicon create karta hai kuch cores ko power off karke taaki power budget fewer cores par concentrate ho sake, unhe better single-thread performance ke liye higher voltage aur frequency par run karne deta hai.

Why can't voltage scale below ~0.7V? :: Is threshold ke neeche, transistors threshold voltage (Vt) limits ki wajah se unreliable ho jaate hain—woh on/off states mein clearly distinguish nahi kar paate, jisse logical errors hote hain.

What is the difference between dynamic and static power?

Dynamic power (αCV²f) tab consume hoti hai jab transistors state switch karte hain. Static power (V×I_leak) leakage current ki wajah se continuously consume hoti hai, chahe transistors switch na kar rahe hon. Modern nodes par static power total power ka 30-50% tak badh gayi hai.

If a chip has 64 cores, 100W TDP, and each core needs 2W when active, what is the dark silicon percentage?

Active cores = ⌊100/2⌋ = 50. Dark silicon = (64-50)/64 = 14/64 = 21.875%.