Power gating and clock gating — Hinglish notes

6.4.4 · Hardware › Power, Thermal & Reliability

Overview

Modern chips idle hone par bhi power burn karte hain. Power gating aur clock gating do fundamental techniques hain jo digital circuits mein dynamic power aur static power reduce karti hain — battery life, thermal limits, aur data-center energy costs ke liye critical hain.

Clock Gating

Yeh Hai Kya

Clock gating ek circuit block ko clock signal disable kar deta hai jab woh block koi useful work nahi kar raha. Combinational logic mein power rehti hai, lekin flip-flops toggle nahi karte, isliye unki internal capacitances ko charge/discharge karne mein koi dynamic power nahi lagti.

Dynamic Power Clock Toggles Par Kyun Depend Karta Hai

Dynamic power yaad karo:

Jab ek flip-flop ka clock input toggle karta hai, internal nodes charge/discharge hote hain chahe data input change na ho. Clock rokne se ( $α \to 0$ us block ke liye), hum un transitions ko eliminate kar dete hain.

Clock Gating Kaise Kaam Karta Hai (Derivation)

Original circuit: Clock har flip-flop tak unconditionally pahunchti hai.
Clock gate insert karo: Ek AND gate global clock ko ek enable signal ke saath combine karta hai: $gated_clk = clk \land enable$
Jab enable = 0: gated_clk constant rehti hai (low), flip-flops apna state hold karte hain, koi dynamic power nahi.
Jab enable = 1: gated_clk clock follow karti hai, circuit normally operate karta hai.

Yeh kaam kyun karta hai: Flip-flops dynamic power tab hi consume karte hain jab unka clock input toggle kare. Constant clock → koi transitions nahi → us block ke liye $α = 0$ .

Worked example Latch-Based Clock Gating (Glitch-Free)

Problem: Naive AND gate glitches create kar sakta hai agar enable clk = 1 ke dauran change ho.

Solution: Enable ko stable rakhne ke liye ek latch insert karo:

Latch enable ko clk ki negative edge par sample karta hai.
Latched enable AND gate ko feed karta hai.
Enable sirf tab change hoti hai jab clk = 0, isliye AND output glitch-free hota hai.

Circuit:

clk ----+----AND----> gated_clk
        |     
     LATCH----+
        |
     enable

Yeh step kyun? Agar enable clk = 1 ke dauran low ho jaaye, toh AND gate ka output mid-cycle drop kar deta hai, ek spurious clock edge create karta hai. Latch ensure karta hai ki enable stable rahe jab clk = 1 ho, false triggers prevent karta hai.

Power Gating

Yeh Hai Kya

Power gating header ya footer switches (large PMOS/NMOS transistors) use karke ek circuit block ki power supply ( $V_{dd}$ ) completely shut off kar deta hai. Yeh dynamic power aur static leakage power dono eliminate karta hai.

Static Power Kyun Matter Karta Hai

Tab bhi jab circuit idle ho (clock gated), transistors mein subthreshold leakage aur gate leakage static power cause karti hai:

Clock gating leakage nahi rokta kyunki $V_{dd}$ abhi bhi applied hai. Power gating $V_{dd}$ cut karta hai, isliye $I_{leak} \to 0$ .

Power Gating Kaise Kaam Karta Hai (Derivation)

Power switch insert karo: Ek PMOS transistor (header switch) $V_{dd}$ aur block ke beech, ya NMOS (footer switch) block aur ground ke beech.
Control signal: Ek sleep signal switch gate drive karta hai.
- sleep = 0: Switch ON, block powered.
- sleep = 1: Switch OFF, block isolated, leakage ≈ 0.
State retention: Jab power down hoti hai registers apni values kho dete hain. Retention flip-flops use karo (slave latch jo always-on rail se powered ho) ya shutdown se pehle state ko memory mein save karo.

Yeh kaam kyun karta hai: $V_{dd}$ disconnect hone se, transistors mein koi voltage nahi → koi leakage paths nahi → $P_{static} \to 0$ .

Worked example GPU Shader Core Ko Power Gate Karna

Scenario: Ek GPU mein 32 shader cores. Gaming workload 8 cores use karta hai; baaki 24 idle hain.

Power gating ke bina:

24 idle cores current leak karte hain: $P_{leak} = 24 \times 50 mW = 1.2 W$ . Power gating ke saath:
24 cores ko header switches use karke turn off karo.
Leakage ~0.01 W tak drop ho jaati hai (sirf switch leakage).
Savings: ~1.19 W.

Wake-up penalty: Jab kisi core ki zaroorat ho:

sleep de-assert karo → power switch on ho jaata hai (10-100 ns).
Pipeline state retention registers se restore karo (aur 100ns).
Total wake-up latency: ~200 ns. Yeh step kyun? OS/driver idle periods predict karta hai (jaise frame render finish, 5 ms ke liye koi kaam nahi). Agar idle time > wake-up time, toh power gating energy bachata hai. Trade-off: latency vs. energy.

Comparison Table

Feature	Clock Gating	Power Gating
Targets	Dynamic power ( $α C V^{2} f$ )	Dynamic + Static power
Mechanism	Flip-flops ko clock disable karo	Switch ke through $V_{dd}$ disconnect karo
State retention	Automatic (flip-flops state hold karte hain)	Retention cells ya save/restore chahiye
Wake-up latency	0 cycles (instant)	10s-100s of ns (switch + restore)
Area overhead	Chhota (AND gates + latch)	Moderate (large power switches + retention)
Leakage reduction	None	~99%
Use case	Short idle periods (μs)	Long idle periods (ms+)

Common Mistakes

Derivation from First Principles: Power Gating Savings

Goal: $T_{sleep}$ time ke liye ek block ko power-gate karne se saved energy quantify karna.

Power gating ke bina:

Dynamic power: $P_{dyn} = α C V^{2} f$ (lekin $α = 0$ agar clock-gated ho).
Static power: $P_{static} = I_{leak} V_{dd}$ .
$T_{sleep}$ mein energy: $E_{no_pg} = P_{static} T_{sleep}$ .

Power gating ke saath:

$t = 0$ par turn off karo, $t = T_{sleep}$ par wake karo.
Sleep ke dauran: $P \approx 0$ (sirf switch leakage, $P_{static}$ ka ~1%).
Wake-up energy: $E_{wake} = C_{block} V_{dd}^{2}$ (saare gates recharge karo).
Total energy: $E_{pg} = E_{wake} + 0.01 P_{static} T_{sleep}$ .

Savings condition: $E_{no_pg} > E_{pg}$ $P_{static} T_{sleep} > C_{block} V_{dd}^{2} + 0.01 P_{static} T_{sleep}$ $0.99 P_{static} T_{sleep} > C_{block} V_{dd}^{2}$ $T_{sleep} > \frac{C _{block} V _{dd}^{2}}{0.99 P _{static}}$

Break-even time $T_{BE}$ define karo:

Example numbers:

$C_{block} = 1 nF$ (ek shader core).
$V_{dd} = 1 V$ .
$P_{static} = 50 mW$ .
$T_{BE} = \frac{1 0 ^{- 9} \times 1 ^{2}}{0.05} = 20 ns$ .

Yeh step kyun? Agar block > 20 ns ke liye idle hai, power gating jeet jaata hai. Chhote idles wake-up par energy waste karte hain. Modern power management controllers idle durations predict karte hain taaki gating policy decide kar sakein.

Recall Feynman Explanation (ELI12)

Imagine karo tumhare ghar mein 20 rooms hain, lekin aaj tum sirf 3 rooms use kar rahe ho. Baaki 20 rooms mein light on chodna bijli waste karna hai, hai na?

Clock gating aisa hai jaise un 17 khaali rooms mein light switch off kar do. Bijli un rooms se abhi bhi connected hai, lekin bulb on-off nahi flash kar raha, isliye tum flashing part mein power waste nahi karte. Lekin wires mein abhi bhi thodi si bijli leak hoti hai (jaise ek phone charger jo plug in hai lekin charge nahi kar raha — phir bhi warm hai).

Power gating aisa hai jaise un 17 rooms ko main power box se unplug kar do. Ab bilkul bijli nahi — na flashing, na leaking. Lekin jab tumhe koi room chahiye, tumhe power box tak jaana padega aur breaker wapas flip karna padega, jo kuch seconds leta hai. Agar tumhe 10 seconds mein room chahiye, toh unplug karna worth nahi hai.

Trick yeh hai: Light switches (clock gating) quick breaks ke liye use karo (lunch), aur unplug (power gating) lambi vacations ke liye (overnight).

Connections

Dynamic and Static Power—Clock gating $P_{dyn}$ mein $α$ target karta hai; power gating $P_{static}$ eliminate karta hai.
Subthreshold Leakage—Kyun power gating 45nm se neeche critical hai.
Retention Flip-Flops—Power-gating ke across state kaise preserve karein.
DVFS (Dynamic Voltage and Frequency Scaling)—Maximum savings ke liye aksar gating ke saath combine hota hai.
Multi-Threshold CMOS—Leakage reduce karne ki ek aur technique (power switches ke liye high- $V_{t}$ transistors).
Hierarchical Clock Distribution—Clock gates kahan insert karein (local vs. global).
Power Management IC (PMIC)—External controller jo gating policies orchestrate karta hai.

Active Recall Flashcards

#flashcards/hardware

Clock gating kya hai? :: Ek circuit block ko clock signal disable karna jab idle ho, AND gates use karke, taaki flip-flop toggles se dynamic power eliminate ho jab logic powered rahe.

Power gating kya hai?

Header/footer switches ke through circuit block se Vdd ya ground disconnect karna taaki dynamic aur static (leakage) dono power eliminate ho, state loss hoti hai jab tak retention cells use na ho.

Clock gating leakage power kyun reduce NAHI karta?

Kyunki Vdd transistors se connected rehta hai, isliye subthreshold aur gate leakage currents tab bhi flow karte rehte hain jab clock rok diya jaaye.

Power gating ke liye break-even time kya hai?

Minimum idle duration

T_{BE} = \frac{C _{block} V _{dd}^{2}}{P _{static}}

jiske liye leakage eliminate karne se saved energy block wapas wake karne ki energy cost se zyada ho.

Retention flip-flop kya hai?

Ek flip-flop jisme ek slave latch hota hai jo always-on Vret rail se powered hota hai, taaki jab main power domain gate off ho tab bhi woh 1 bit state retain kar sake.

Clock gating mein latch kyun use karte hain?

Glitches prevent karne ke liye: latch enable signal ko clock ki negative edge par sample karta hai, ensure karta hai ki clk = 1 hone par enable stable rahe, enable transitions se false clock edges avoid hoti hain.

Clock gating __ power reduce karta hai, power gating ___ power reduce karta hai.

dynamic; static (leakage)

Power gating ke liye wake-up latency trade-off kya hai?

Power gating mein 10-100 ns wake-up delay hoti hai (switch on + state restore), isliye yeh tab hi beneficial hai jab idle time is delay se zyada ho; clock gating mein zero latency hoti hai.