Clock tree synthesis — Hardware notes

WHAT is CTS?

Before CTS, the clock is an ideal net (assumed zero delay). After CTS, it becomes a real tree with buffers, real wire RC, and real arrival times.

Root = clock source (PLL output / clock port).
Leaves/Sinks = clock pins of flip-flops, latches, memories.
Internal nodes = inserted clock buffers/inverters.

The three key quantities (WHY they matter)

WHY skew is the villain: timing between a launching FF and a capturing FF depends directly on the difference of their clock arrival times, not the absolute latency.

HOW skew eats your timing budget (derive from scratch)

Consider data launched by FF1 (clock arrival $t_1$ ) and captured by FF2 (clock arrival $t_2$ ), one clock period $T$ apart.

Setup check (data must arrive before the next edge):

Data leaves FF1 at $t_1 + t_{cq}$ (clock-to-Q), travels through combinational logic $t_{logic}$ , and must satisfy the setup time $t_{su}$ before FF2's capturing edge at $t_2 + T$ :

$t_1 + t_{cq} + t_{logic} + t_{su} \le t_2 + T$

Rearrange, letting skew $= t_2 - t_1$ :

$\boxed{t_{cq} + t_{logic} + t_{su} \le T + (t_2 - t_1)}$

Hold check (data must NOT arrive too early, before the same edge captures):

$t_1 + t_{cq} + t_{cd} \ge t_2 + t_{hold}$

where $t_{cd}$ is the minimum (contamination) logic delay. Rearranging:

$\boxed{t_{cq} + t_{cd} \ge t_{hold} + (t_2 - t_1)}$

HOW CTS actually builds the tree

Common structures:

H-tree / X-tree — a geometrically symmetric fractal. Every leaf is the same wire distance from the root ⇒ naturally low skew. Great for regular arrays (like clock spines of CPUs), wasteful for irregular placements.
Buffered clock tree (algorithmic) — tools cluster nearby sinks, insert buffers to balance load, and recursively merge. The classic algorithm is DME (Deferred-Merge Embedding), built on zero-skew merging.

Zero-skew merge point (derive the balance)

Two subtrees with delays (to their sinks) $d_1$ and $d_2$ are joined. We place the merge point splitting a wire of total length $L$ into $l_1$ (to node 1) and $l_2 = L - l_1$ (to node 2). Using the Elmore delay for a wire segment of length $l$ with resistance $r$ and capacitance $c$ per unit length driving a load cap $C$ :

$t_{wire}(l, C) = r\,l\left(\frac{c\,l}{2} + C\right)$

For zero skew we need equal delay from the merge point to each side:

$d_1 + t_{wire}(l_1, C_1) = d_2 + t_{wire}(l_2, C_2)$

Substituting and setting the two delays equal gives the merge-point location $l_1$ (solving a quadratic). For the simplified case ignoring the $\frac{cl^2}{2}$ self term:

$d_1 + r\,l_1 C_1 = d_2 + r\,l_2 C_2,\quad l_1 + l_2 = L$ $\Rightarrow l_1 = \frac{(d_2 - d_1) + r L C_2}{r(C_1 + C_2)}$

Worked Example 1 — Skew and the setup budget

Given: $T = 2\text{ ns}$ , $t_{cq}=0.2$ , $t_{logic}=1.5$ , $t_{su}=0.1$ ns. Launch clock arrives at $t_1 = 0.5$ , capture at $t_2 = 0.6$ ns.

Setup slack $= (T + t_2 - t_1) - (t_{cq}+t_{logic}+t_{su})$

Why this step? Slack = available − required; positive means we meet timing.

$= (2 + 0.6 - 0.5) - (0.2+1.5+0.1) = 2.1 - 1.8 = +0.3\text{ ns}$ ✅ meets setup.

Now check hold with $t_{cd}=0.3$ , $t_{hold}=0.15$ ns: Required: $t_{cq}+t_{cd} \ge t_{hold} + (t_2-t_1)$ $0.2 + 0.3 = 0.5 \ge 0.15 + 0.1 = 0.25$ ✅ passes.

Why this step? We must verify hold with the same skew — positive skew shrank the hold margin.

Worked Example 2 — Zero-skew merge point

Given: Two sinks. Left has accumulated delay $d_1 = 40$ ps, right $d_2 = 10$ ps. Wire per-unit $r = 0.1\ \Omega/\mu m$ , sink caps $C_1 = C_2 = 20\ \text{fF}$ , total merge wire $L = 100\ \mu m$ .

Using $l_1 = \dfrac{(d_2 - d_1) + rLC_2}{r(C_1+C_2)}$ :

Why this step? We want the split that equalizes root-to-sink delay.

Numerator (keep consistent units, use ps/fF/Ω/µm): $rLC_2 = 0.1\times100\times20 = 200$ (ps-like scaled units), $(d_2-d_1) = -30$ . $l_1 = \frac{-30 + 200}{0.1\times40} = \frac{170}{4} = 42.5\ \mu m$

So the merge point sits 42.5 µm from sink 1 (the slower side gets less wire). Since $0 \le 42.5 \le 100$ , no snaking needed. ✅

Worked Example 3 — Why an H-tree gives (near) zero skew

In an H-tree every path from root to leaf traverses the same number of segments of the same lengths by construction. Since delay depends only on the traversed RC, equal geometry ⇒ equal delay ⇒ skew ≈ 0 (ignoring process variation).

Why this step? Symmetry replaces per-net balancing — it's a structural solution vs. an algorithmic one.

Active Recall

Recall Explain each before revealing

What is the difference between insertion delay and skew?
Why does positive skew help setup but hurt hold?
Where does the DME merge point move, toward the fast or slow subtree?
Why is CTS power-critical?

Recall Feynman: explain to a 12-year-old

You're playing "everybody jump at the same time!" You (the boss) shout GO. But if your friends stand at different distances, the sound reaches them at different times, so they jump raggedly. To fix it, you place helpers (buffers) who re-shout the word, and you make the paths equally long so the word reaches everyone together. The little differences in when they hear it = skew. The total travel time from you to a friend = insertion delay. Building this network of helpers and equal paths is clock tree synthesis.

Connections

Static Timing Analysis — CTS makes clock arrivals real so STA can be accurate.
Setup and Hold Time — the constraints CTS must satisfy.
Elmore Delay Model — the RC delay math behind merge points.
Placement (VLSI) — sink locations come from placement; CTS runs after it.
Useful Skew / Clock Skew Scheduling — deliberate skew for timing closure.
Clock Gating and Power — CTS handles gated clock enables and dominates dynamic power.
On-Chip Variation (OCV) — why real skew margins exceed nominal skew.

What is Clock Tree Synthesis?

The physical-design step that inserts buffers and routes the clock net from source to all flip-flop clock pins, minimizing skew and insertion delay while meeting slew/cap/fanout limits.

Define insertion delay (clock latency).

The time for the clock edge to propagate from the clock root to a given sink (leaf).

Define clock skew.

The difference in insertion delay (clock arrival time) between two flip-flops; global skew = max latency − min latency.

Why does positive skew (capture later than launch) help setup?

The setup equation becomes

t_{cq}+t_{logic}+t_{su} \le T + (t_2-t_1)

, so later capture adds slack.

Why does positive skew hurt hold?

Hold requires

t_{cq}+t_{cd} \ge t_{hold} + (t_2-t_1)

; later capture increases the required minimum data delay.

What is an H-tree and why is its skew low?

A geometrically symmetric fractal clock distribution where every root-to-leaf path has identical length/segments, so delays match structurally.

In DME/zero-skew merging, which way does the merge point move?

Toward the faster (smaller-delay) subtree, so its extra wire delay equalizes arrival times.

What is 'useful skew'?

Intentionally scheduling non-zero skew to borrow time on critical paths (delay capture for setup, advance for hold) rather than forcing zero skew everywhere.

Why is the clock tree power-critical?

It's the highest-toggling net on the chip; dynamic power

P=\alpha C V^2 f

means buffers and clock cap dominate switching power.

When is hold fixing typically done relative to CTS?

After CTS, once clock arrivals are real, by inserting delay buffers on data paths.

Give the Elmore delay of a wire of length

l

(r,c per unit) driving load C.

t = r\,l\,(cl/2 + C)

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Socho clock ek "GO!" signal hai jo chip ke andar hazaaron flip-flops ko ek saath jump karwana chahta hai. Problem yeh hai ki source se har flip-flop tak wire ki lambai alag hai, isliye signal alag-alag time par pahunchta hai. Is time difference ko skew kehte hain, aur source se kisi ek flip-flop tak jitna time lagta hai use insertion delay (latency) kehte hain. Clock Tree Synthesis ka kaam hai: beech mein buffers daalna aur wires ko balance karna taaki sabko signal lagbhag ek saath mile.

Skew ka funda double-edged hai. Agar capture wale flip-flop ka clock thoda late aaye (positive skew), toh setup ke liye extra time mil jaata hai — yeh helpful hai. Lekin wahi late clock hold ko todd sakta hai. Isiliye CTS zero skew nahi, balki balanced/useful skew target karta hai. Setup equation yaad rakho: $t_{cq}+t_{logic}+t_{su} \le T + \text{skew}$ , aur hold: $t_{cq}+t_{cd} \ge t_{hold} + \text{skew}$ .

Tree banane ke do tareeke hain: H-tree (symmetric shape jismein har path barabar lamba hota hai, isliye skew apne aap kam) aur algorithmic buffered tree jismein tool DME/zero-skew merge use karta hai. Merge point hamesha fast (kam delay) side ki taraf khiskta hai taaki extra wire delay se dono side barabar ho jaaye.

Ek important baat: clock chip ka sabse zyada toggle karne wala net hai, isliye power ( $P=\alpha C V^2 f$ ) yahin sabse zyada jalti hai — bade buffers har jagah lagana galat hai. Aur haan, CTS ke baad hold violations aa sakti hain, jinhe baad mein data path par buffer daal ke fix karte hain. Yaad rakho SLIP: Skew, Latency, Insertion, Power.

Test yourself — VLSI Design

Connections