The historical scaling parameter is the ==minimum feature size λ==. In classic
λ-based (scalable) design rules, every rule is expressed as a multiple of
λ so a whole design can be ported to a new process just by rescaling λ.
Note: this scalable approach is largely a teaching/legacy convention — modern advanced CMOS
nodes (e.g. "7 nm") do not use a single λ; there the node name is a marketing/generation
label and the foundry ships a large table of explicit, absolute (nanometre) micro-rules instead.
Let's derive the four canonical rule types from the single idea:
"masks can misalign and light/etch blurs edges by some tolerance."
Let mask misalignment tolerance be t, and litho/etch edge blur be b (each printed edge
moves by up to b from its drawn position).
1. Minimum width wmin.
A drawn line of width w shrinks by up to b on each edge during etch, so the printed
width is ≈w−2b. To guarantee the line survives with some safe width ws:
w≥ws+2b≡wmin
2. Minimum spacing smin.
Two lines separated by s each grow by b toward each other during over-exposure, closing
the gap to s−2b. To guarantee they never merge:
s≥2b+(safety)≡smin
3. Minimum enclosure / overlap emin.
A via (contact) must stay inside its metal even in the worst case, where two effects stack:
(a) the two masks shift relative to each other by up to t, and (b) blur can grow the via edge
outward by bwhile shrinking the metal edge inward by b. The metal must therefore extend
past the drawn via by at least the sum of these worst-case movements on each side:
e≥t+2b≡emin
4. Minimum extension.
Where poly crosses diffusion to form a transistor gate, poly must extend past the diffusion
edge so that neither misalignment t nor blur b ever leaves an unfinished gate (which would
short source to drain):
extension≥t+b≡extmin
5. Minimum area Amin (a "printability" rule).
Very small shapes fail to resolve at all under diffraction, independent of width/spacing. A shape
of area A must exceed the smallest reliably-printable patch Amin:
A≥Amin
You built a Lego castle on graph paper and want a factory to stamp it into plastic.
The factory says: "our machine can't make a wall thinner than 2 squares, and if two walls
are less than 1 square apart they'll melt into one blob." DRC is you going over your
drawing with a ruler, checking every wall is thick enough and every gap is wide enough,
before you send it. If you skip this, the factory happily prints a broken, melted castle.
That a layout's geometry obeys the foundry's design rules (widths, spacings, enclosures, extensions, areas) — geometry only, not logic.
DRC vs LVS?
DRC checks geometric design rules; LVS checks that the layout matches the schematic netlist (logic/connectivity). Both are required.
Why does a minimum spacing rule exist?
Litho/etch blur makes edges grow; too-close shapes merge into a short. Spacing guarantees a safe gap.
Why does a via enclosure rule exist?
Masks can misalign by tolerance t AND blur can move edges by b; metal must surround the via by ≥ t+2b so the contact never opens.
Enclosure per side for a centered via?
(metal_size − via_size)/2.
What is λ in design rules?
A legacy scaling parameter; classic scalable rules are multiples of λ so designs port across nodes. Modern advanced nodes (e.g. "7 nm") do NOT use a single λ.
What is a "sliver" violation?
A shape that passes width/spacing but is below minimum area — fails to print due to the diffraction limit.
Can a logically-correct circuit fail DRC?
Yes — DRC is purely geometric; correct logic can still have illegal spacings/enclosures.
Dekho, DRC ka matlab hai Design Rule Checking. Jab tum ek chip ka layout banate ho, toh
wo bas kuch polygons hote hain alag-alag layers (metal, poly, diffusion, via) pe. Ab fab
(factory) ki apni physical limits hoti hain — light blur karti hai, masks thoda shift ho
jaate hain, etching edges ko kha jaati hai. Isliye foundry kuch rules deti hai: minimum
width, minimum spacing, minimum enclosure, minimum extension, minimum area. DRC ek automated
tool hai jo tumhare poore layout ko scan karke check karta hai ki koi rule toota toh nahi.
Sabse important baat: DRC sirf geometry dekhta hai, logic nahi. Matlab tumhara circuit
bilkul sahi kaam kar raha ho simulation mein, phir bhi DRC fail ho sakta hai agar do wires
bahut paas hain ya via ke upar metal poori tarah cover nahi kar raha. Logic wala check alag
hota hai — usko LVS kehte hain. Tape-out (chip banwane) se pehle dono pass hone zaroori hain.
Har rule ke peeche ek physical reason hai. Enclosure ka rule dekho — via ke upar metal
ko sirf misalignment t ke liye nahi, balki blur b ke liye bhi extra jagah chahiye, isliye
e≥t+2b. Ek aur cheez: λ (lambda) ek purani teaching-convention hai jahan saare
rules λ ke multiples mein hote hain, lekin modern "7 nm" jaise nodes mein aisa single
λ nahi hota — wahan foundry ek badi table deti hai exact nanometre rules ki. Mnemonic
yaad rakho — WSEEA (Width, Spacing, Enclosure, Extension, Area).
