Level 2 — RecallVLSI Design

VLSI Design

⏱ 30 minutes50 marksprintable — key stays hidden on paper

Chapter: 4.2 VLSI Design Level: 2 (Recall / Standard Problems / Short Derivations) Time Limit: 30 minutes Total Marks: 50

Instructions

Answer all questions.
Show working for numerical questions.
Use $...$ notation where mathematical expressions are required.

Q1. State Moore's Law. If a chip has $2 \times 10^9$ transistors in year 2020 and Moore's Law implies a doubling every 2 years, how many transistors would be expected in year 2026? (5 marks)

Q2. Dennard scaling relates transistor dimensions and voltage to power density. State the two key scaling assumptions of Dennard scaling and give one physical reason why it broke down around the mid-2000s. (5 marks)

Q3. Compare full custom and standard cell design approaches with respect to (a) design effort, (b) performance/area, and (c) time-to-market. Give one row per criterion. (6 marks)

Q4. Define a standard cell library. List three items of information typically characterized for each cell in the library. (5 marks)

Q5. Briefly explain the following back-end design steps in one sentence each: (a) Floorplanning, (b) Placement, (c) Routing, (d) Power planning. (4 marks)

Q6. Explain clock tree synthesis (CTS). Define clock skew and clock latency (insertion delay). (6 marks)

Q7. Distinguish between DRC (Design Rule Checking) and LVS (Layout Versus Schematic). State what each verifies. (5 marks)

Q8. A power grid segment carries a current of $0.5\ \text{A}$ through a metal resistance of $0.2\ \Omega$ . Calculate the IR drop. If the supply is $1.0\ \text{V}$ and the cell requires at least $0.85\ \text{V}$ to operate correctly, does this segment meet the requirement? (5 marks)

Q9. In the context of DFT, define a scan chain and briefly state the purpose of BIST (Built-In Self-Test). (5 marks)

Q10. Name two low-power design techniques and explain in one line how each reduces power. Also state which power component (dynamic or static/leakage) each primarily targets. (4 marks)

End of Paper

Answer keyMark scheme & solutions

Q1. (5 marks)

Moore's Law: the number of transistors on an integrated circuit doubles approximately every two years (originally ~every 18–24 months). (2)
Number of doublings from 2020 to 2026 = $6/2 = 3$ . (1)
$N = 2\times10^9 \times 2^3 = 2\times10^9 \times 8 = 1.6\times10^{10}$ transistors. (2) Why: Each 2-year interval multiplies count by 2; three intervals give factor $2^3=8$ .

Q2. (5 marks)

Assumption 1: As transistor dimensions scale by factor $1/k$ , the supply voltage $V$ and threshold voltage also scale by $1/k$ . (1.5)
Assumption 2: Doping and other parameters scale so that the electric field stays constant, keeping power density roughly constant as area shrinks. (1.5)
Breakdown reason (any one): Threshold voltage could not be lowered further without leakage (subthreshold + gate) current rising exponentially; hence voltage stopped scaling, so power density increased. (2)

Q3. (6 marks) — 2 marks per correct row.

Criterion	Full Custom	Standard Cell
Design effort	Very high (manual layout of transistors)	Lower (automated, reuses pre-designed cells)
Performance/Area	Optimal — best speed, smallest area, lowest power	Good but sub-optimal (fixed cell heights/overhead)
Time-to-market	Long / slow	Short / fast

Why: Full custom trades engineering time for optimal silicon; standard cell trades some efficiency for automation and speed.

Q4. (5 marks)

Definition: A collection of pre-designed, pre-characterized, and pre-verified logic gates/cells (layouts + models) provided at fixed height, used by synthesis and P&R tools. (2)
Any three characterized items (1 each, max 3): timing (delay, transition), input capacitance, power/leakage, physical layout (LEF/abstract), function/logical model (Verilog), area, drive strengths.

Q5. (4 marks) — 1 mark each.

(a) Floorplanning: defining chip dimensions and the placement of major blocks, I/O, and macros.
(b) Placement: assigning exact physical locations to standard cells within the core.
(c) Routing: connecting the placed cells with metal interconnect according to the netlist.
(d) Power planning: creating power/ground rings, straps, and rails to deliver current with acceptable IR drop.

Q6. (6 marks)

CTS: The process of building a balanced clock distribution network (buffers/inverters) that delivers the clock to all sequential elements with minimal and controlled skew. (2)
Clock skew: the difference in clock arrival times between two flip-flops (spatial difference). (2)
Clock latency / insertion delay: the total delay from the clock source to a clock sink (flip-flop clock pin). (2)

Q7. (5 marks)

DRC: verifies that the physical layout obeys the foundry's geometric manufacturing rules (spacing, width, enclosure, density). Checks manufacturability. (2.5)
LVS: verifies that the layout's extracted netlist matches the schematic/reference netlist (correct connectivity and devices). Checks functional/topological correctness. (2.5)

Q8. (5 marks)

IR drop $= I \times R = 0.5 \times 0.2 = 0.1\ \text{V}$ . (2)
Voltage at cell $= 1.0 - 0.1 = 0.9\ \text{V}$ . (2)
$0.9\ \text{V} \ge 0.85\ \text{V}$ , so the segment meets the requirement. (1)

Q9. (5 marks)

Scan chain: sequential elements (flip-flops) modified into scan flip-flops connected in a shift-register chain, allowing test patterns to be shifted in and captured responses shifted out, improving controllability/observability. (3)
BIST: on-chip circuitry that generates test patterns and analyzes responses internally (e.g., LFSR + MISR), enabling the chip to test itself without external ATE. (2)

Q10. (4 marks) — 2 marks per technique (name + mechanism + power type).

Clock gating: disables the clock to idle registers/blocks, removing switching activity → reduces dynamic power.
Power gating: switches off supply to inactive blocks via sleep transistors → reduces static/leakage power.
(Also acceptable: DVFS reduces dynamic power; multi-Vt cells reduce leakage.)

[
  {"claim":"Moore's Law: 2e9 transistors doubling every 2 years over 6 years gives 1.6e10","code":"N0=2*10**9; years=6; doublings=years/2; N=N0*2**doublings; result=(N==1.6*10**10)"},
  {"claim":"IR drop = 0.5A * 0.2ohm = 0.1V","code":"I=Rational(1,2); R=Rational(1,5); drop=I*R; result=(drop==Rational(1,10))"},
  {"claim":"Cell voltage after IR drop meets 0.85V requirement","code":"Vsup=Rational(1,1); drop=Rational(1,10); Vcell=Vsup-drop; result=(Vcell>=Rational(85,100))"},
  {"claim":"Number of doublings from 2020 to 2026 is 3","code":"d=(2026-2020)/2; result=(d==3)"}
]