VLSI Design

Question 1 (12 marks)

(a) Under constant-field scaling, dimensions ($L, W, t_{ox}$) and voltage $V$ scale by $1/k$; doping increases by $k$.

• Gate capacitance: $C = \varepsilon \frac{W L}{t_{ox}}$. Scaling: $C \to \varepsilon \frac{(W/k)(L/k)}{t_{ox}/k} = \frac{C}{k}$. So $C$ scales by $1/k$. (2)
• Delay: $\tau \sim \frac{CV}{I}$. Current $I \sim \frac{W}{L}\frac{(V-V_{th})^2}{...}$ scales by $1/k$. Then $\tau \sim \frac{(C/k)(V/k)}{I/k} = \frac{CV}{Ik} = \frac{\tau}{k}$. Delay scales by $1/k$ (gates get faster). (2)
• Dynamic power per transistor: $P = C V^2 f$. With $C\to C/k$, $V\to V/k$, $f\to kf$ (since delay improves): $P \to \frac{C}{k}\cdot\frac{V^2}{k^2}\cdot kf = \frac{P}{k^2}$. Power per device scales by $1/k^2$. (2)

(b) Power density: Transistor count per unit area increases by $k^2$ (area per device $\to 1/k^2$). Power per device $\to 1/k^2$. Power density $= \frac{P/k^2 \times k^2}{\text{area}} =$ constant. Field, and hence reliability, stays constant. (2)

(c) Breakdown mechanisms (2 for mechanisms, 2 for consequence):

• Threshold voltage / subthreshold leakage: $V_{th}$ cannot scale down proportionally without exponentially increasing subthreshold leakage current, so supply voltage $V_{DD}$ stopped scaling.
• Gate-oxide tunneling leakage: Ultra-thin $t_{ox}$ causes gate leakage; oxide thickness could no longer scale.
• Consequence: With $V$ fixed, dynamic power density rose with frequency, causing the "power wall" → clock frequencies plateaued (~3–4 GHz). Industry shifted to multi-core parallelism instead of frequency scaling.

Question 2 (8 marks)

(a) Moore's Law: transistor count on an IC doubles roughly every 2 years. (1) $N(t) = N_0 \cdot 2^{t/2}$ where $t$ is years and doubling period is 2 years. (2)

(b) $N_0 = 2\times10^9$, $t = 8$ years: $N(8) = 2\times10^9 \cdot 2^{8/2} = 2\times10^9 \cdot 2^4 = 2\times10^9 \cdot 16 = 3.2\times10^{10}$ So 32 billion transistors. (3)

(c) Any two (1 each): lithography limits / EUV cost and complexity; rising fabrication cost per node; leakage and power constraints; approaching atomic dimensions; wire (interconnect) scaling not keeping pace; diminishing performance return.

Question 3 (12 marks)

(a) Floorplanning & power planning: Define chip/block dimensions, place macros/IP, define I/O pin locations, and create the power distribution network (rings, straps, rails) to deliver clean $V_{DD}/V_{SS}$. Sets area, aspect ratio, and reserves routing resources. (3)

(b) Placement: Assign physical (x,y) locations to standard cells to minimize wirelength and congestion while meeting timing; legalizes cells onto rows. (2)

(c) CTS: Builds a balanced clock distribution network (buffers/inverters) to deliver the clock to all sinks. (2)

• Skew = difference in clock arrival times between two sinks (e.g., launch vs capture FF). (1)
• Insertion delay (latency) = delay from clock source to a sink. CTS is done after placement because clock buffer placement/loading depends on where FFs sit; it is done before routing because clock nets must be routed with priority and the added buffers change the netlist that signal routing must handle. (1)

(d) Routing: Connect all pins with actual metal wires across layers (global then detailed routing) obeying design rules. (1)

(e) (2, any two get full, all three ideal)

• DRC: checks layout obeys foundry geometric manufacturing rules (spacing, width, enclosure).
• LVS: verifies extracted layout netlist matches the schematic/logical netlist.
• Parasitic extraction (RC): extracts resistance and capacitance of interconnect for accurate post-layout timing/signal-integrity analysis.

Question 4 (10 marks)

(a) Setup constraint (capture edge must arrive after data is stable): (2) $t_{cq} + t_{logic} + t_{setup} \le T + t_{skew}$

(b) Solve for skew margin: (3) $t_{skew} \ge t_{cq}+t_{logic}+t_{setup} - T = 0.10+0.70+0.08 - 1.0 = -0.12\text{ ns}$ The constraint is satisfied even at $t_{skew}=0$ with 0.12 ns slack. Positive skew helps setup; there is no upper bound imposed by setup here — path passes with 0.12 ns slack at zero skew. Maximum required is that skew $\ge -0.12$ ns, i.e., any positive skew is fine for setup. Setup slack = 0.12 ns.

(c) Hold constraint: (2) $t_{cq} + t_{logic,min} \ge t_{hold} + t_{skew}$ Positive skew (capture later) means data can race through and change the captured value before the (delayed) capture edge stabilizes → worsens hold. (1) Max positive skew: (2) $t_{skew} \le t_{cq}+t_{logic,min} - t_{hold} = 0.16 - 0.05 = 0.11\text{ ns}$ So maximum tolerated positive skew = 0.11 ns.

Question 5 (10 marks)

(a) IR drop $= I\times R = 0.120 \times 0.5 = 0.06\text{ V}$. (2) Load voltage $= 0.90 - 0.06 = 0.84\text{ V}$. (1)

(b) Required min = 0.85 V, actual = 0.84 V → fails by 0.01 V (margin $= 0.84-0.85 = -0.01$ V). (2)

(c) Any three (1 each): widen power straps / add metal; increase number of power pads/bumps; use higher/thicker metal layers for power; add more power straps (denser mesh); add decoupling capacitors; reduce peak current via clock/power gating scheduling.

(d) (2)

• Static IR drop: based on average/steady-state currents, no switching timing — a DC analysis.
• Dynamic IR drop: accounts for time-varying switching currents and simultaneous switching, capturing transient voltage droop (worst-case with decap effects).

Question 6 (8 marks)

(a) A scan flip-flop replaces a normal FF with one having a multiplexer on its data input (adds a scan-in port and scan-enable). (1) Two modes: (2)

• Functional/capture mode: FF captures normal logic data (scan-enable low).
• Shift/scan mode: FFs form a shift register; test vectors shifted in and responses shifted out (scan-enable high).

(b) Single chain of length $L=5000$, patterns $P=400$. Each pattern: shift in $L$ cycles + 1 capture cycle; shifting out overlaps with shifting in the next pattern. (1) $\text{Cycles} \approx P\times(L+1) + L = 400\times5001 + 5000$ $= 2{,}000{,}400 + 5000 = 2{,}005{,}400 \text{ cycles}$ (Simpler approximation $P\times(L+1)\approx 2.0\times10^6$ cycles also accepted.) (2)

(c) Any one (2): BIST needs no expensive external ATE / less test data volume; enables at-speed and in-field/self-test; reduces test time and pin/bandwidth requirements; on-chip pattern generation (LFSR) and response compaction (MISR).

[
  {"claim":"Moore Q2b: 2e9 * 2**(8/2) = 3.2e10","code":"N=2*10**9*2**(Rational(8,2)); result = (N==Integer(32)*10**9)"},
  {"claim":"Q4b setup: tcq+tlogic+tsetup-T = -0.12","code":"val=Rational(10,100)+Rational(70,100)+Rational(8,100)-1; result = (val==Rational(-12,100))"},
  {"claim":"Q4c hold max skew: 0.16-0.05 = 0.11","code":"val=Rational(16,100)-Rational(5,100); result = (val==Rational(11,100))"},
  {"claim":"Q5a IR drop 0.12*0.5=0.06 and load 0.84","code":"ir=Rational(12,100)*Rational(5,10); vl=Rational(90,100)-ir; result = (ir==Rational(6,100)) and (vl==Rational(84,100))"},
  {"claim":"Q6b cycles: 400*(5000+1)+5000 = 2005400","code":"c=400*(5000+1)+5000; result = (c==2005400)"}
]