VLSI Design

Question 1

(a) Ideal Dennard (6 marks)

Scaling by $\kappa$:

• Capacitance $C \propto \varepsilon A_{gate}/t_{ox}$; both plate area and $t_{ox}$ scale $\Rightarrow C \propto (1/\kappa^2)/(1/\kappa) = 1/\kappa$. (1)
• Voltage $V \to V/\kappa$. (1)
• Current $I \propto \frac{W}{L}\mu C_{ox}(V-V_{th})^2$. With $W,L\to /\kappa$ (ratio const), $C_{ox}\propto\kappa$, and $V\to/\kappa$: $I \propto \kappa \cdot (1/\kappa)^2 = 1/\kappa$. (1)
• Delay $\tau = CV/I = (1/\kappa)(1/\kappa)/(1/\kappa) = 1/\kappa \Rightarrow f \propto \kappa$. (1)

Then per-device power: $P_{dyn}=\alpha C V^2 f \propto (1/\kappa)(1/\kappa^2)(\kappa)=1/\kappa^2.$ Device area $A \propto 1/\kappa^2$. Hence $\frac{P}{A}\propto \frac{1/\kappa^2}{1/\kappa^2}=1 \quad\text{(constant).}\ \blacksquare$ (2)

(b) Constant-V breakdown (6 marks)

Now $C\propto 1/\kappa$, $f\propto\kappa$ (delay still $\tau=CV/I$; with $V$ const and $I\propto\kappa$: $\tau=(1/\kappa)(1)/(\kappa)=1/\kappa^2$, so $f\propto\kappa^2$ if drive scales that way — but conventionally with $V$ fixed and short-channel $I\propto\kappa$, keep $f\propto\kappa$; either derivation accepted if consistent). Using the standard result with $f\propto\kappa$: $P_{dyn}\propto C V^2 f \propto (1/\kappa)(1)(\kappa)=1 \ \text{per device}.$ (3) Area still $1/\kappa^2$, so $\frac{P}{A}\propto \frac{1}{1/\kappa^2}=\kappa^2.$ Power density rises as $\kappa^2$ — each new node packs more devices per unit area at the same power each, so heat flux grows quadratically. Cooling and reliability cannot keep pace: this is the power wall, forcing frequency stagnation (~3–4 GHz) and the shift to multicore. (3)

(c) Leakage & power gating (8 marks)

Lowering $V_{th}$ by $\Delta V_{th}=100$ mV raises $(V_{gs}-V_{th})$ by 100 mV: $\text{factor}=10^{\,\Delta V_{th}/S}=10^{100/90}=10^{1.111}=12.9\times.$ (4) So static leakage increases ~12.9× per 100 mV of $V_{th}$ reduction. (1)

Implication: Clock gating stops dynamic switching power ($\alpha\to0$) but leaves the block powered, so leakage keeps flowing. Post-Dennard, $V_{th}$ was pushed low to preserve overdrive under non-scaling $V_{dd}$, making leakage a dominant fraction of total power (order of the same magnitude as dynamic). Only power gating — physically disconnecting supply via header/footer sleep transistors — cuts the exponential leakage term to near zero for idle blocks. Hence clock gating alone is insufficient. (3)

Question 2

(a) Timing inequalities & slacks (8 marks)

Setup: $t_{cq}+t_{comb,max}+t_{su}\le T+t_{skew}$ $0.05+0.72+0.08=0.85\le 1.0+t_{skew}\Rightarrow t_{skew}\ge -0.15\text{ ns.}$ (2)

Hold: $t_{cq}+t_{comb,min}\ge t_h+t_{skew}$ $0.05+0.05=0.10\ge 0.06+t_{skew}\Rightarrow t_{skew}\le 0.04\text{ ns.}$ (2)

Allowable skew: $-0.15\le t_{skew}\le 0.04$ ns — non-empty, so closable. (1)

At $t_{skew}=0$:

• Setup slack $=T - (t_{cq}+t_{comb,max}+t_{su})=1.0-0.85=+0.15$ ns. (1.5)
• Hold slack $=(t_{cq}+t_{comb,min})-t_h=0.10-0.06=+0.04$ ns. (1.5)

Both positive → design meets timing.

(b) H-tree & useful skew (7 marks)

H-tree: geometric self-similarity gives equal path length from root to every leaf, so wire+buffer insertion delays match ⇒ nominally zero skew; symmetry also makes it robust to systematic process gradients. (2)

Useful skew: intentionally delaying the capture clock (positive $t_{skew}$) borrows time into the setup budget (RHS $T+t_{skew}$ grows), letting a slow path close at higher $f$, at the cost of hold margin. It redistributes slack across the timing graph. (2)

Balancing setup and hold slacks as functions of $t_{skew}$:

• Setup slack $=0.15+t_{skew}$ (increases with skew)
• Hold slack $=0.04-t_{skew}$ (decreases with skew)

Max–min at equality: $0.15+t_{skew}=0.04-t_{skew}\Rightarrow 2t_{skew}=-0.11\Rightarrow t_{skew}=-0.055$ ns. Balanced slack $=0.15+(-0.055)=0.095$ ns each. (3)

(c) Skew algorithm (5 marks)

computeMaxSkew(root):
    # DFS: accumulate root-to-leaf insertion delay
    leafDelays = []
    stack = [(root, 0)]
    while stack:
        node, d = stack.pop()
        if node.isLeaf: leafDelays.append(d)
        for (child, w) in node.edges:
            stack.push((child, d + w))
    return max(leafDelays) - min(leafDelays)   # worst skew

Time complexity: $O(V+E)=O(n)$ for a tree with $n$ nodes (single traversal). (3)

CTS reduces skew by inserting/sizing buffers on the shorter/faster leaf paths to raise their insertion delay up to the longest path's — i.e. it balances insertion delay so max(leafDelays)-min(leafDelays)→0, pulling all leaf delays toward a common target latency. (2)

Question 3

(a) Elmore delay (8 marks)

Lumped: $t_d=0.69\,RC=0.69\cdot 200\cdot 40\times10^{-15}=0.69\cdot 8.0\times10^{-12}=5.52\times10^{-12}=5.52$ ps. (3)

Distributed proof: segment $i$ (from source) sees resistance $iR/n$ driving capacitance $C/n$. Elmore delay: $t_d=0.69\sum_{i=1}^{n}\left(\frac{iR}{n}\right)\frac{C}{n}=0.69\,\frac{RC}{n^2}\sum_{i=1}^{n} i=0.69\,\frac{RC}{n^2}\cdot\frac{n(n+1)}{2}.$ $=0.69\,RC\cdot\frac{n+1}{2n}\xrightarrow{n\to\infty}0.69\cdot\frac{RC}{2}.\ \blacksquare$ (3)

Significance: a distributed line is 2× faster than the lumped model, and delay scales with $L^2$ (both R and C grow with length). Repeaters break a long wire into $k$ segments, converting $L^2$ dependence into $\approx L^2/k$ plus buffer delay, minimized at an optimal segment count. (2)

(b) Crosstalk (6 marks)

Charge sharing / capacitive divider: $\Delta V = V_{dd}\frac{C_c}{C_c+C_g}=0.9\cdot\frac{8}{8+24}=0.9\cdot\frac{8}{32}=0.9\cdot0.25=0.225\text{ V}.$ (3)

Noise margin $=0.2\cdot0.9=0.18$ V. Since $0.225>0.18$, signal integrity is violated (glitch exceeds margin). (1)

Two mitigations (any two): shielding (ground/power lines between nets), increasing spacing (lowers $C_c$), reducing parallel run length, stronger victim driver, or wire ordering/repeater staggering. (2)

(c) IR drop + DFT (6 marks)

IR drop $=I R_{grid}=1.5\cdot0.015=0.0225$ V $=22.5$ mV. Effective $V_{dd}=0.9-0.0225=0.8775$ V. (2)

Delay $\propto (V_{dd}-V_{th})^{-\gamma}$. Overdrive nominal $=0.9-0.3=0.6$; drooped $=0.8775-0.3=0.5775$. $\frac{t_{droop}}{t_{nom}}=\left(\frac{0.6}{0.5775}\right)^{1.3}=(1.03896)^{1.3}=1.0510.$ ≈ 5.1% delay increase. (2)

Scan-shift IR drop: during scan shift, essentially all flops toggle every cycle (data ripples through the chain), giving far higher and more uniform switching activity than typical functional workloads — this raises average current draw and worsens IR droop/di-dt beyond functional worst case. Mitigations: lower shift clock frequency (less $f$-driven current), partition scan-enable so only sub-chains shift at a time, or use low-power scan reordering to reduce shift-in transitions. (2)

[
  {"claim":"Leakage increase factor for 100mV Vth drop, S=90mV/dec ~12.9x","code":"val=10**(100/90); result = abs(val-12.9)<0.2"},
  {"claim":"Setup slack 0.15ns, hold slack 0.04ns, balance skew -0.055ns, balanced slack 0.095ns","code":"setup=1.0-(0.05+0.72+0.08); hold=(0.05+0.05)-0.06; sk=Rational(-11,200); bal=setup+float(s