Level 1 — RecognitionVLSI Design

VLSI Design

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Chapter: 4.2 VLSI Design Level: 1 (Recognition) Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each)

Q1. Moore's Law originally predicted that the number of transistors on a chip would:

(a) double roughly every 24 months at constant cost
(b) halve every 18 months
(c) grow linearly with clock frequency
(d) remain constant while power increased

Q2. Under classical Dennard scaling, when transistor dimensions scale by a factor $1/k$ , power density stays approximately:

(a) proportional to $k$
(b) constant
(c) proportional to $k^2$
(d) proportional to $1/k$

Q3. Which of the following is a primary reason Dennard scaling broke down (~2005)?

(a) transistors became too large
(b) supply voltage ( $V_{dd}$ ) could no longer scale down due to leakage/threshold limits
(c) copper interconnect was banned
(d) clock trees became unnecessary

Q4. Compared to full-custom design, standard-cell design primarily offers:

(a) the highest possible transistor density and performance
(b) faster design time and easier automation at some area/performance cost
(c) no need for place and route
(d) elimination of DRC

Q5. In the physical design flow, Clock Tree Synthesis (CTS) is mainly performed to:

(a) reduce leakage current
(b) minimize clock skew and balance clock delays to sequential elements
(c) extract parasitic capacitance
(d) verify layout matches schematic

Q6. LVS (Layout vs Schematic) checks that:

(a) the layout obeys geometric spacing rules
(b) the extracted netlist of the layout matches the intended schematic netlist
(c) IR drop is within budget
(d) scan chains are correctly ordered

Q7. DRC (Design Rule Checking) verifies:

(a) functional equivalence of RTL and gates
(b) geometric/manufacturing constraints such as minimum width and spacing
(c) electrical connectivity to the schematic
(d) test coverage percentage

Q8. Parasitic (RC) extraction produces information used primarily for:

(a) accurate timing and signal-integrity analysis
(b) generating the standard-cell layout
(c) assigning pin names
(d) writing the testbench

Q9. Crosstalk in signal integrity is caused mainly by:

(a) resistive IR drop only
(b) coupling capacitance/inductance between neighbouring nets
(c) clock skew
(d) scan insertion

Q10. IR drop in a power grid refers to:

(a) voltage droop caused by current flowing through the resistance of the power network
(b) leakage of the clock net
(c) inductive ringing on I/O pads
(d) skew between clock branches

Q11. A scan chain converts flip-flops into a shift register during test mode primarily to:

(a) reduce dynamic power
(b) improve controllability and observability of internal nodes
(c) balance the clock tree
(d) reduce die area

Q12. Clock gating reduces power by:

(a) lowering the supply voltage of idle blocks
(b) disabling the clock to registers when their outputs are not changing
(c) shutting off power rails entirely
(d) inserting scan flops

Q13. Power gating differs from clock gating because power gating:

(a) only affects the clock net
(b) shuts off supply to idle blocks to cut leakage (static) power
(c) increases switching activity
(d) is done during CTS

Section B — Matching (1 mark each, Q14 = 6 marks total)

Q14. Match each design step (1–6) to its purpose (A–F). (6 marks)

#	Step		Purpose
1	Floorplanning	A	Add self-test logic that generates patterns on-chip
2	Place & Route	B	Define block placement, I/O, and power ring structure
3	Power planning	C	Position gates and connect them with metal wires
4	BIST	D	Build power rails/straps to deliver current with low IR drop
5	Standard cell library	E	Characterized set of pre-designed logic gates
6	DFT	F	Insert structures (e.g., scan) to make testing feasible

Section C — True/False WITH Justification (2 marks each: 1 verdict + 1 justification)

Q15. "Dennard scaling breaking down means Moore's Law (transistor count doubling) also stopped immediately." — True/False, justify.

Q16. "In standard-cell libraries, all cells share a fixed cell height so they can be placed in rows." — True/False, justify.

Q17. "DRC-clean layout guarantees the circuit is functionally correct." — True/False, justify.

Q18. "Power gating primarily reduces dynamic switching power rather than leakage." — True/False, justify.

Q19. "Adding scan chains has zero cost in area and timing." — True/False, justify.

Total: 13 (MCQ) + 6 (matching) + 10 (T/F) = 30 marks

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1 — (a). Moore observed transistor count doubling at roughly constant cost per die (~every ~2 years in the modern statement). Why: it is an economic/density trend, not a frequency law.

Q2 — (b) constant. Under Dennard scaling, scaling dimensions and voltage by $1/k$ keeps power density constant. Why: capacitance, voltage and delay scale so that power per unit area is invariant.

Q3 — (b). $V_{dd}$ /threshold voltage stopped scaling because lower $V_{th}$ causes exponential subthreshold leakage. Why: leakage-dominated power broke the constant-power-density assumption.

Q4 — (b). Standard cells trade some density/performance for automation and faster turnaround. Why: pre-characterized cells + EDA flow speed design.

Q5 — (b). CTS balances insertion delay to minimize skew. Why: skew directly eats into timing margin.

Q6 — (b). LVS compares extracted layout netlist to schematic netlist. Why: ensures the drawn layout implements the intended connectivity.

Q7 — (b). DRC checks geometric manufacturing rules. Why: guarantees manufacturability, not function.

Q8 — (a). RC extraction feeds timing/SI analysis. Why: real wire R and C determine delay and noise.

Q9 — (b). Coupling capacitance/inductance between adjacent nets. Why: aggressor switching injects noise onto victim nets.

Q10 — (a). $V = I \times R$ droop across the power network resistance. Why: delivered voltage sags under current load.

Q11 — (b). Improves controllability/observability. Why: shifting values in/out lets ATPG set and read internal states.

Q12 — (b). Disables clock to idle registers. Why: stops unnecessary clock/register switching (dynamic power).

Q13 — (b). Power gating cuts supply to reduce leakage. Why: removing rail voltage eliminates static leakage current.

Section B

Q14 (6 marks — 1 each): 1→B, 2→C, 3→D, 4→A, 5→E, 6→F. Why: Floorplan defines block/power topology; P&R places and wires; power planning builds the grid; BIST self-generates test patterns; the cell library is characterized gates; DFT adds testability structures.

Section C (2 marks each: 1 verdict, 1 justification)

Q15 — FALSE. (verdict 1) Dennard scaling (power-density) breakdown is distinct from Moore's Law (transistor count). (justification 1) Transistor counts kept increasing after ~2005; what stopped was easy frequency/power-density gains, prompting the multicore shift.

Q16 — TRUE. (1) Standard cells use a fixed (or fixed multiple) cell height. (1) Uniform height lets cells abut in placement rows sharing power/ground rails, enabling automated row-based P&R.

Q17 — FALSE. (1) DRC only checks geometry/manufacturability. (1) Functional correctness requires logic verification/LVS + timing; a DRC-clean layout can still be functionally wrong.

Q18 — FALSE. (1) Power gating targets leakage (static) power. (1) It shuts off supply to idle blocks; dynamic switching power is instead reduced by clock gating / voltage scaling.

Q19 — FALSE. (1) Scan insertion has overhead. (1) Scan flops are larger and add mux delay + routing, costing area and some timing (though enabling manufacturing test).

[
  {"claim":"Dennard: scaling dims and voltage by 1/k keeps power density constant (P/A invariant)","code":"k=symbols('k',positive=True); C=1/k; V=1/k; f=k; P=C*V**2*f; area=(1/k)**2; density=simplify(P/area); result = (density==1)"},
  {"claim":"IR drop V=I*R: 2A through 0.05 ohm gives 0.1V","code":"I=2; R=Rational(5,100); V=I*R; result=(V==Rational(1,10))"},
  {"claim":"Moore doubling: from 2000 to 2010 (~5 doublings at 2yr) multiplies count by 32","code":"years=10; doublings=years/2; factor=2**doublings; result=(factor==32)"},
  {"claim":"Dynamic power scales with V^2: halving V quarters dynamic power","code":"V=symbols('V',positive=True); Pfull=V**2; Phalf=(V/2)**2; ratio=simplify(Phalf/Pfull); result=(ratio==Rational(1,4))"}
]