Historical scaling parameter ==minimum feature size λ== hai. Classic λ-based (scalable) design rules mein, har rule λ ke multiple ke roop mein express hota hai taaki poora design ek naye process pe port kiya ja sake sirf λ ko rescale karke.
Note: ye scalable approach kaafi hadd tak ek teaching/legacy convention hai — modern advanced CMOS nodes (jaise "7 nm") ek single λuse nahi karte; wahan node ka naam ek marketing/generation label hai aur foundry ek badi table of explicit, absolute (nanometre) micro-rules ship karti hai.
Chalo hum chaaro canonical rule types ek single idea se derive karte hain:
"Masks misalign ho sakte hain aur light/etch edges ko kuch tolerance se blur kar deta hai."
Maano mask misalignment tolerance t hai, aur litho/etch edge blur b hai (har printed edge apni drawn position se b tak move kar sakti hai).
1. Minimum width wmin.
Ek drawn line jiska width w hai, etch ke dauran har edge se b tak shrink ho sakti hai, toh printed width ≈w−2b hoti hai. Ye guarantee karne ke liye ki line kuch safe width ws ke saath survive kare:
w≥ws+2b≡wmin
2. Minimum spacing smin.
Do lines jo s se alag hain, over-exposure ke dauran ek doosre ki taraf b se grow karti hain, gap ko s−2b tak close kar deti hain. Ye guarantee karne ke liye ki woh kabhi merge na hon:
s≥2b+(safety)≡smin
3. Minimum enclosure / overlap emin.
Ek via (contact) ko apni metal ke andar rehna chahiye chahe worst case mein bhi, jahan do effects stack ho jaate hain:
(a) do masks ek doosre ke relative t tak shift ho jaate hain, aur (b) blur via edge ko b se baahir grow kar sakta hai jabki metal edge b se andar shrink ho sakti hai. Metal ko isliye drawn via se past ek minimum tak extend karna chahiye, jo in worst-case movements ka har side pe sum ho:
e≥t+2b≡emin
4. Minimum extension.
Jahan poly, diffusion ko cross karti hai transistor gate banane ke liye, poly ko diffusion edge se past extend karna chahiye taaki na misalignment t aur na blur b kabhi ek unfinished gate chhod de (jo source ko drain se short kar deta):
extension≥t+b≡extmin
5. Minimum area Amin (ek "printability" rule).
Bahut chhoti shapes diffraction ki wajah se bilkul resolve nahi hoti, width/spacing se independent. Ek shape jiska area A hai woh smallest reliably-printable patch Amin se zyada hona chahiye:
A≥Amin
Tumne graph paper pe ek Lego castle banaya aur chahte ho ek factory use plastic mein stamp kare.
Factory kehti hai: "hamare machine se 2 squares se patli wall nahi ban sakti, aur agar do walls 1 square se kam door hon toh woh melt hokar ek blob ban jaayengi." DRC matlab hai tum apni drawing ko ruler se jaanch rahe ho, har wall ko kaafi mota aur har gap ko kaafi wide check kar rahe ho, bhejne se pehle. Agar ye skip karo, toh factory khushi se ek toota hua, pigha hua castle print kar degi.
Ki ek layout ki geometry foundry ke design rules (widths, spacings, enclosures, extensions, areas) ko obey karti hai — sirf geometry, logic nahi.
DRC vs LVS?
DRC geometric design rules check karta hai; LVS check karta hai ki layout schematic netlist (logic/connectivity) se match karta hai. Dono required hain.
Minimum spacing rule kyun exist karti hai?
Litho/etch blur edges ko grow karta hai; bahut paas ki shapes short banakar merge ho jaati hain. Spacing ek safe gap guarantee karta hai.
Via enclosure rule kyun exist karti hai?
Masks tolerance t se misalign ho sakte hain AUR blur edges ko b se move kar sakta hai; metal ko via ko ≥ t+2b se surround karna chahiye taaki contact kabhi na khole.
Centered via ke liye enclosure per side?
(metal_size − via_size)/2.
Design rules mein λ kya hai?
Ek legacy scaling parameter; classic scalable rules λ ke multiples hain taaki designs nodes across port ho sakein. Modern advanced nodes (jaise "7 nm") ek single λ USE NAHI KARTE.
"Sliver" violation kya hoti hai?
Ek shape jo width/spacing pass kar leti hai lekin minimum area se neeche hai — diffraction limit ki wajah se print nahi hoti.
Kya ek logically-correct circuit DRC fail kar sakta hai?
