Serial vs parallel signaling (SerDes)

What Are Parallel and Serial Signaling?

Why Did We Shift from Parallel to Serial?

The Parallel Bottleneck

In the 1980s-90s, parallel buses dominated (ISA, PCI, SCSI). But as clock speeds increased, three physics problems emerged:

1. Skew Accumulation

When you send 8 bits simultaneously on8 traces, small differences in trace length, PCB layer, or driver strength cause bits to arrive at different times. This timing difference is skew.

Formula Skew Limit on Parallel Bandwidth

For a parallel bus with $n$ wires, if the skew between any two wires is $\Delta t_{skew}$ , the maximum clock period is: $T_{clk} \geq \Delta t_{skew} +_{setup} + t_{hold}$

Derivation from first principles:

The receiver samples all $n$ bits with one clock edge
For correct sampling, all bits must be stable during the setup/hold window
If one bit arrives early and another late, the difference $\Delta t_{skew}$ "eats into" the clock period
Setup time $t_{setup}$ is how long before the clock edge data must be stable
Hold time $t_{hold}$ is how long after the clock edge data must remain stable
Therefore: $T_{clk} = t_{valid} + t_{setup} + t_{hold}$ where $t_{valid} \geq \Delta t_{skew}$

Maximum frequency: $f_{max} = \frac{1}{T_{clk}} \leq \frac{1}{\Delta t_{skew} + t_{setup} + t_{hold}}$

Why this matters: At 10 cm trace length, speed-of-light delay is ~0.5 ns. With 1 mm length mismatch, skew is ~5 ps. At 1 GHz (period = 1 ns), 5 ps skew is manageable. At 10 GHz (period = 0.1 ns = 100 ps), 5 ps is 5% of the clock period—unacceptable.

Worked example Parallel Bus Skew Calculation

PCI-X 133 MHz, 64-bit bus:

64 data lines, 1 clock line
Assume PCB trace length mismatch: 5 mm worst-case between shortest and longest trace
Signal propagation: $v \approx 0.6c = 1.8 \times 10^8$ m/s (typical FR-4 PCB)
Skew: $\Delta t = \frac{5 \times 10^{-3}}{1.8 \times 10^8} \approx 28$ ps Clock period at 133 MHz: $T = \frac{1}{133 \times 10^6} \approx 7.5$ ns

Skew as % of period: $\frac{28}{7500} \approx 0.37\%$ — manageable.

Now try1 GHz: $T =1$ ns, skew = 28 ps → $\frac{28}{1000} = 2.8\%$ — marginal.

At 5 GHz: $T = 0.2$ ns = 200 ps, skew = 28 ps → $14\%$ of the clock period lost to skew! This forces either slower clocks or expensive skew-compensation (not scalable).

2. Crosstalk

Formula Crosstalk Voltage

When two parallel traces carry signals, the aggressor line induces voltage on the victim line via capacitive and inductive coupling: $V_{crosstalk} \approx C_{mutual} \frac{dV_{aggressor}}{dt}$ Derivation:

Two parallel traces have mutual capacitance $C_{mutual}$ (pF/cm range)
Current in aggressor: $i_{aggressor} = C_{mutual} \frac{dV}{dt}$ (displacement current)
This returns through victim trace, causing voltage drop across its impedance
For fast edges (high $\frac{dV}{dt}$ ), crosstalk voltage increases linearly Why this kills parallel: With8 or 64 lines switching simultaneously, crosstalk is data-dependent. Pattern "0101" causes maximum crosstalk. You must slow down edges ( $\frac{dV}{dt} \downarrow$ ), which limits bandwidth.

3. Electromagnetic Interference (EMI)

Parallel buses with many traces switching together act as antennas. The radiated power scales with frequency and number of simultaneous edges:

$P_{radiated} \propto f^2 \cdot n \cdot l^2$

where $n$ = number of traces, $l$ = trace length, $f$ = frequency. FCC limits force designers to add shielding/filtering, increasing cost.

The Serial Solution

Serial signaling with differential pairs solves all three:

No skew: Only1 data lane (plus its complement), so no multi-wire alignment problem
Differential immunity: Crosstalk appears as common-mode noise, rejected by the receiver
Lower EMI: Differential currents cancel, reducing radiation

Formula Serial Bandwidth Calculation

A serial link running at symbol rate $R_s$ (Gbaud) with encoding overhead $\eta$ achieves data rate: $R_{data} = R_s \cdot \eta \cdot b$ where $b$ = bits per symbol (usually 1 for NRZ, 2 for PAM-4).

Derivation:

Symbol rate $R_s$ is the number of voltage transitions per second
Each symbol carries $b$ bits of information (log₂ of voltage levels)
Encoding (8b/10b, 64b/66b) adds overhead: for every $k$ data bits, we send $n$ encoded bits
Efficiency $\eta = \frac{k}{n}$ (8b/10b: $\eta = 0.8$ ; 64b/66b: $\eta = 0.97$ ) Example: PCIe Gen3 uses 8.0 GT/s (gigatransfers/sec) with 128b/130b encoding: $R_{data} = 8.0 \times 10^9 \times \frac{128}{130} \times 1 \approx 7.877 \text{ Gbps per lane}$

16 lanes (x16): $16 \times 7.877 \approx 126$ Gbps total—far exceding parallel buses with manageable pin count.

How SerDes Works

Serializer Architecture

Figure — Serial vs parallel signaling (SerDes)

Step-by-step operation:

Parallel Load: At slow clock $f_{low}$ , load $n$ bits into shift register
Fast Clock Multiplication: PLL generates $f_{high} = n \cdot f_{low}$
Shift Out: Each $f_{high}$ cycle, shift out 1 bit onto differential TX lines
Differential Driver: Converts single-ended logic to differential voltage (e.g., ±400 mV)

Deserializer Architecture

The receiver must:

Recover Clock: Incoming data has no separate clock wire. Use CDR to extract clock from data edges.
Sample Data: Sample at mid-bit (not at transitions) for maximum margin.
Align to Byte Boundary: Find the start of each $n$ -bit group using special patterns (comma characters in8b/10b).

When to Use Parallel vs. Serial

Criterion	Parallel	Serial (SerDes)
Frequency	< 500 MHz	> 1 GHz
Distance	< 10 cm (on-chip, PCB)	cm to meters
Pin count	High (8, 16, 64 wires)	Low (1 diff pair = 2 pins)
Cost	Low (simple logic)	High (PLL, CDR, analog)
Power	Low at low speed	Higher (high-speed analog)
Use cases	DRAM interfaces (DDR), on-chip buses	PCIe, USB, SATA, Ethernet, chiplet I/O

Common Mistakes

Active Recall Prompts

Recall Explain SerDes to a 12-year-old

Imagine you're moving a stack of 10 books from one room to another. You have two choices: Option 1 (Parallel): Carry all 10 books in one trip. Fast, right? But the stack is heavy and wobbly—you might drop them, and you need wide doorway.

Option 2 (Serial): Carry 1 book at a time, but run really fast. Yes, you make 10 trips, but you're so fast that you finish before the "carry all 10" person even gets through the door. Plus, you never drop anything because1 book is easy to control.

SerDes is Option 2. Computers used to send data like Option 1 (parallel wires, many bits at once), but wires are like narrow hallways—they interfere with each other, causing "dropped books" (errors). So now we send data one bit at a time (serial) on a single super-fast wire. The trick is the "serializer" packs the bits into a single stream, and the "deserializer" unpacks them on the other end. It's faster, fewer wires, and fewer mistakes!

Connections

Clock Domain Crossing (CDC): SerDes deserializer creates a new clock domain; needs FIFOs to cross into system clock.
PCIe Protocol: Uses SerDes with 128b/130b encoding; lanes can be ganged (x1, x4, x16).
Eye Diagrams: Visual tool to measure SerDes link quality (jitter, noise, ISI).
Equalization (CTLE, DFE): High-speed SerDes use equalization to combat ISI from PCB traces.
8b/10b Encoding: Common SerDes encoding scheme; trades20% bandwidth for DC balance and comma symbols.
PLL and Clock Synthesis: Serializer needs PLL to multiply clock; deserializer CDR is a form of PLL.
Differential Signaling: SerDes almost always uses differential pairs (LVDS, CML).
DDR Memory Interface: Uses parallel signaling with source-synchronous clocking to manage skew.

#flashcards/hardware

What is the key advantage of serial signaling over parallel at high frequencies? :: Serial avoids skew accumulation across multiple wires, allowing much higher bit rates on a single differential pair.

What does SerDes stand for and what does it do?

Serializer-Deserializer; converts parallel data to high-speed serial for transmission and back to parallel at the receiver.

Why does parallel bus skew become unmanageable above ~1 GHz?

At 1 GHz, period = 1 ns. Even10 ps skew (1% of period) from trace length mismatch consumes setup/hold margin. At 10 GHz, 10 ps is 10% of the period—impractical.

What is Clock-Data Recovery (CDR) and why is it needed in SerDes?

CDR extracts the clock from the incoming serial data stream by detecting edges. Needed because serial links don't send a separate clock wire—reduces pin count and skew.

How does differential signaling help SerDes reduce crosstalk?

Crosstalk from nearby traces appears as common-mode noise on both wires of the differential pair. The receiver subtracts the two signals, canceling common-mode and preserving only the differential signal.

What is the data rate formula for a serial link with encoding overhead?

R_{data} = R_s \cdot \eta \cdot b

where

R_s

is symbol rate,

\eta

is encoding efficiency (e.g., 128/130 for 128b/130b), and

b

is bits per symbol (1 for NRZ, 2 for PAM-4).

Why does EMI radiated power scale as

f^2 \cdot n \cdot l^2

for parallel buses?

Higher frequency

f

means faster current changes (more antenna efficiency),

n

traces act as

n

antennas, and longer trace length

l

increases effective antenna aperture. Each factor multiplies together.

At what approximate frequency does the industry crossover from parallel to serial occur and why?

Around 500 MHz to 1 GHz. Below this, parallel is cheaper. Above, skew and crosstalk make parallel impractical compared to SerDes cost.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, yahan basic tradeoff yeh samajhna hai ki data bhejne ke do tareeke hain. Parallel matlab tum ek saath multiple bits alag-alag wires pe bhejte ho — jaise 8 pages ek saath photocopy karke dena. Serial matlab tum ek-ek bit ek hi wire (differential pair) pe bhejte ho, lekin bahut fast speed pe. Pehle zamane mein sabko laga ki parallel behtar hai kyunki ek saath zyada bits jaa rahe hain, lekin jab clock speeds badhne lage, tab physics ne problems create kar di.

Ab why-it-matters: parallel mein sabse bada issue hai skew. Jab 8 wires pe ek saath bits bhejte ho, toh chhoti-chhoti trace length ki differences ki wajah se bits alag-alag time pe pahunchte hain. Receiver toh sab bits ek hi clock edge pe sample karta hai, isliye jab tak saare bits stable na ho, sampling galat ho jaayegi. High speeds pe (jaise 5 GHz), yeh skew clock period ka 14% tak kha jaata hai — matlab bilkul unacceptable. Iske upar crosstalk ka problem bhi aata hai, jahan ek wire ka signal doosri wire pe voltage induce kar deta hai. In dono problems ko 8 wires pe manage karna bahut mushkil aur mehnga hai.

Isliye engineers ne serial ki taraf shift kiya, aur yahan SerDes (Serializer-Deserializer) chips ka kaam aata hai. Chip ke andar data parallel form mein hota hai, phir SerDes usse serial mein convert karke ek hi high-speed line pe bhejta hai, aur doosri taraf wapas parallel bana deta hai. Iska fayda yeh hai ki ek wire ko really fast chalana aasan hai — na skew ka jhamela, na 8 machines ko sync karne ki tension. Isliye aaj ke PCIe, USB, SATA, Ethernet — sab serial signaling use karte hain. Yeh concept modern hardware ki backbone hai, toh ise achhe se pakad lena.

What Are Parallel and Serial Signaling?

Why Did We Shift from Parallel to Serial?

The Parallel Bottleneck

The Serial Solution

How SerDes Works

Serializer Architecture

Deserializer Architecture

When to Use Parallel vs. Serial

Common Mistakes

Active Recall Prompts

Connections

Concept Map

Hinglish (regional understanding)

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Interconnects, Buses & SoC

Connections