Serial vs parallel signaling (SerDes): Question bank

Vocabulary you need first

Read these before the quiz — several traps below turn on knowing them precisely.

True or false — justify

Every claim below is either true or false. Say "true" or "false" first, then give the reason.

Serial links are faster than parallel because electrons move faster on a single wire.

False — electrons don't move faster. Serial wins because one lane needs no cross-wire skew alignment, so its clock can run far higher than a parallel bus limited by its worst-aligned pair.

A 1-lane serial link at 8 GT/s always beats a 64-bit parallel bus at 133 MHz in raw throughput.

False — 64 × 133 MHz ≈ 8.5 Gbps of parallel payload roughly ties one 8 GT/s lane (≈ 7.9 Gbps), so a single lane is only comparable; serial wins by adding many independent lanes without the skew penalty.

Differential signaling removes crosstalk entirely.

False — it converts most external noise into common-mode noise that the receiver subtracts away, but coupling between pairs and imperfect balance still leave residual crosstalk.

A serial link needs a dedicated clock wire alongside the data pair.

False — that is exactly what serial avoids; the clock is embedded in the data edges and rebuilt by clock-data recovery (CDR), which is why data patterns must guarantee frequent transitions.

8b/10b encoding makes the link faster.

False — it makes it slower per raw bit (only

η = 0.8

payload: 8 useful bits per 10 transmitted), but it guarantees transition density and DC balance so the CDR can lock and the receiver stays biased correctly. See 8b/10b Encoding.

Wider parallel buses always give more bandwidth than narrower ones.

False — beyond a point, adding wires increases skew spread, crosstalk, and pin count, forcing a slower clock; the net bandwidth can fall, which is why the industry went serial.

PAM-4 doubles the data rate at the same symbol rate for free.

False — it packs 2 bits per symbol, but the four voltage levels sit closer together, so the eye is smaller and it demands stronger equalization and lower noise. See Eye Diagrams and Equalization (CTLE, DFE).

A closed eye diagram means the physical wire is broken.

False — a closed eye means bit periods overlap so badly (from skew, ISI, jitter, or noise) that the sampler can't find a clean point; the wire may be fine but under-equalized. See Eye Diagrams.

The transmitter and receiver must share the exact same crystal frequency for a serial link to work.

False — they run on independent crystals with tiny frequency differences; the CDR continuously tracks the incoming edge rate so the receiver's sampling clock follows the transmitter's, absorbing the drift.

Skew between data wires is a problem on a single serial lane too, just smaller.

False — a single lane has only one differential pair, so there is no inter-wire data skew at all; skew only reappears when you must align multiple lanes (e.g. PCIe x16 lane-to-lane deskew). See PCIe Protocol.

Spot the error

Each statement contains one wrong word or claim. Name it and fix it.

"Setup time is how long after the clock edge the data must stay stable."

Wrong — that describes hold time; setup time is how long before the edge the data must already be stable.

"At higher clock rates, a fixed 28 ps skew becomes a smaller fraction of the clock period."

Wrong — higher rate means shorter period, so the same 28 ps becomes a larger fraction; that is precisely why parallel buses stall.

"CDR samples the data exactly on the signal edges for maximum accuracy."

Wrong — it samples at mid-bit, as far from the edges as possible, because edges are where transitions and jitter live; the eye is widest in the middle.

"Crosstalk depends only on trace length, not on the data pattern."

Wrong — crosstalk scales with

\frac{d V}{d t}

of the aggressor, so a fast-switching pattern like 0101 injects far more than a static one; it is data-dependent.

"A serializer runs its shift register at the same clock as the parallel input."

Wrong — it multiplies the clock: an

n : 1

serializer shifts at

n \times f_{l o w}

using a PLL, so 8 bits leave in the time one parallel word arrives. See PLL and Clock Synthesis.

"PCIe Gen3's 128b/130b encoding wastes 20% of the bandwidth like 8b/10b."

Wrong — 128b/130b overhead is only

2/130 \approx 1.5%

(

η \approx 0.985

); 8b/10b wastes 20%. Newer generations traded coding overhead for scrambling. See PCIe Protocol.

"EMI from a parallel bus is independent of how many lines switch together."

Wrong — radiated power scales with the number of simultaneously switching traces (

P \propto n

), so many aligned edges radiate far more than one differential pair whose currents cancel.

"Equalization adds signal energy to make the link go faster."

Wrong — equalization doesn't add energy; it reshapes the frequency response (boosting high frequencies the channel attenuated) to reopen the eye. See Equalization (CTLE, DFE).

Why questions

Answer with the mechanism, not just the outcome.

Why does a serial link need frequent bit transitions in the data?

Because the receiver's CDR extracts its clock from data edges; a long run of identical bits gives no edges, so the recovered clock drifts and sampling loses lock — hence line coding forces transitions.

Why does differential signaling reduce EMI compared to single-ended?

The two wires carry equal-and-opposite currents, so their radiated fields largely cancel in the far field, dramatically lowering the antenna effect of the trace pair. See Differential Signaling.

Why did DDR memory stay parallel while PCIe went serial?

DDR needs very low latency and short, matched, tightly-controlled traces where skew is manageable and the point-to-point distance is small; serialization overhead (SerDes latency, encoding) would hurt memory's latency-critical access. See DDR Memory Interface.

Why must the sampling clock phase error stay below half a bit period?

If the phase error exceeds

\frac{T _{bi t}}{2}

(half of one bit slot

T_{bi t} = \frac{1}{R _{s}}

), the sampling instant crosses into the next bit's window, so the receiver latches the wrong symbol — the CDR feedback loop exists to hold that error near zero.

Why does crosstalk get worse with faster signal edges?

Coupling is proportional to

\frac{d V}{d t}

; a sharper edge means a larger rate of voltage change, inducing a bigger current and voltage on the neighbouring victim trace.

Why can't you just keep widening a parallel bus to beat serial?

More wires multiply skew spread, crosstalk victims, EMI sources, and package pins simultaneously, forcing the shared clock down — the aggregate cost and the skew ceiling grow faster than the bandwidth benefit.

Why does the eye diagram narrow as the channel gets longer?

Longer channels attenuate and delay high-frequency content more, spreading each symbol into its neighbours (inter-symbol interference), which collapses the vertical and horizontal eye opening. See Eye Diagrams.

Edge cases

Boundary and degenerate scenarios the topic quietly assumes away.

What happens on a serial link if the data is a constant stream of 1s forever?

With no transitions the CDR starves for edges and drifts; this is why encoders (8b/10b, scrambling) guarantee a maximum run length so a pathological all-ones payload can never appear on the wire.

If two parallel traces have zero length mismatch, is skew zero?

Not necessarily — skew also comes from different driver strengths, PCB layer permittivity, via count, and loading; equal length removes only the propagation-delay component.

At a very low clock rate, is a parallel bus better than serial?

Often yes — when the period dwarfs the skew and crosstalk is negligible, parallel gives high throughput with simple, low-latency, no-encoding logic; that regime is exactly where legacy parallel buses lived.

What is the CDR doing during a long idle period with no traffic?

With no edges it holds its last locked phase/frequency open-loop and slowly drifts; links send idle/training sequences precisely so the CDR keeps seeing edges and stays locked.

If skew equals exactly the setup-plus-hold budget with zero data-valid time, what happens?

The valid window collapses to nothing — there is no instant where all bits are simultaneously stable for a full setup+hold, so the receiver cannot reliably sample; the bus has hit its hard frequency ceiling.

For a single serial lane, can lane-to-lane skew ever occur?

No — "lane-to-lane" skew is undefined for one lane; it only appears in multi-lane links (like PCIe x8/x16) where independent CDRs recover slightly different phases and a deskew buffer realigns them. See PCIe Protocol.

Recall Quick self-test

Name the three physics problems that killed high-speed parallel buses. ::: Skew accumulation across wires, data-dependent crosstalk between traces, and EMI from many simultaneously switching lines. What single mechanism lets a serial receiver work with no clock wire? ::: Clock-data recovery (CDR), which rebuilds the sampling clock from the data's own edges. Why is 8b/10b's 20% overhead worth paying? ::: It guarantees transition density and DC balance so the CDR stays locked and the receiver stays biased — reliability bought with bandwidth. What is the difference between GT/s and Gbps? ::: GT/s is the symbol (transfer) rate on the wire; Gbps is the useful payload bit rate after subtracting encoding overhead — GT/s ≥ Gbps.