Serial vs parallel signaling (SerDes): Visual walkthrough

This is the visual companion to the parent SerDes note. Read that first for the big-picture callouts; here we go slow and picture-first.

Step 1 — A bit is a voltage that takes time to travel

WHAT. Before "skew" or "bandwidth" can mean anything, we need one honest picture: a single wire, and a voltage that is either high (a 1) or low (a 0). That high/low pattern travels down the wire like a wave — it is not instant.

WHY. Every problem parallel signaling has comes from this one fact: electricity is not infinitely fast. If it were instant, all wires would agree perfectly and this whole page would be blank. So we start here.

PICTURE. Look at the copper trace below. The orange pulse is a 1 moving left-to-right. The label $v$ is its speed.

Figure — Serial vs parallel signaling (SerDes)

The time a bit needs to cross a trace of length $l$ is just distance over speed:

$t_{fly} = \frac{l}{v}$

$l$ — how long the copper trace is (metres).
$v$ — the crawl speed from above.
$t_{fly}$ — "flight time", how long the bit is in transit.

Step 2 — Two wires, two lengths → the bits disagree

WHAT. Now put two wires side by side and send one bit down each at the same instant. If the wires are different lengths, the two bits arrive at different times.

WHY. A parallel bus sends many bits together and reads them with one clock tick. That only works if they all show up together. So the moment two wires differ in length, we have a timing gap — and we must measure it.

PICTURE. Below, the teal wire is a hair longer than the orange wire. Same launch time, but the longer bit lands later. The gap between the two landings is the star of this whole page.

Step 3 — The clock has to wait for the slowest bit

WHAT. The receiver latches all the bits on one clock edge. For that latch to read correct values, every bit must be sitting still (stable) in a little window around the edge.

WHY. A latch (flip-flop) is picky. It needs the data steady for a moment before the edge (call it $t_{setup}$ ) and steady for a moment after (call it $t_{hold}$ ). If any bit is still wobbling because it arrived late, the read is garbage.

PICTURE. The green band is the "stable window" the latch demands. The late (teal) bit slides in and shrinks the safe time. Notice how skew literally pushes the window's start later.

Adding it up, one clock period must be long enough to (a) let the skewed bits all settle, and (b) honour the setup + hold window:

Flip it over to read the top speed. Why flip? Frequency is just "ticks per second", the reciprocal of "seconds per tick":

$f_{m a x} = \frac{1}{T _{clk}} \leq \frac{1}{Δ t _{skew} + t _{setup} + t _{hold}}$

$f_{m a x}$ — the fastest the bus can legally clock.
The bigger $Δ t_{skew}$ gets, the smaller $f_{m a x}$ gets. Skew is a speed ceiling.

Step 4 — Plug in real copper: skew grows into a monster

WHAT. We compute $Δ t_{skew}$ for a real-ish board and compare it against the clock period at three speeds.

WHY. A formula is abstract until you see the percentages. The whole "why did the industry abandon parallel" story is one table of percentages.

PICTURE. The bar chart shows the clock period as the full bar; the orange chunk is the slice eaten by skew. Watch the orange slice swallow the bar as we crank the clock.

Worked example Skew for a 5 mm mismatch

Length mismatch $Δ l = 5 mm = 5 \times 1 0^{- 3}$ m, speed $v = 1.8 \times 1 0^{8}$ m/s: $Δ t_{skew} = \frac{5 \times 1 0 ^{- 3}}{1.8 \times 1 0 ^{8}} \approx 2.78 \times 1 0^{- 11} s = 27.8 ps$ Now compare to one clock period $T = 1/ f$ at three speeds:

Clock $f$	Period $T$	Skew	Skew as $%$ of $T$
$133$ MHz	$7519$ ps	$27.8$ ps	$0.37%$ ✅
$1$ GHz	$1000$ ps	$27.8$ ps	$2.78%$ ⚠️
$5$ GHz	$200$ ps	$27.8$ ps	$13.9%$ ❌

Step 5 — Serial deletes the problem by having one lane

WHAT. Serial signaling sends the bits one after another on a single differential pair (two wires carrying opposite copies of the same signal). With only one data lane, there is no second wire to disagree with — inter-wire skew is structurally gone.

WHY. You can't have a length mismatch between lanes if there's only one lane. We didn't fix skew; we deleted its home. (See Differential Signaling for why the pair also shrugs off noise.)

PICTURE. Top: 8 nervous parallel wires that must agree. Bottom: one confident serial pair streaming bits in time. The clock is recovered from the data edges by a circuit called CDR instead of shipped on its own wire.

But serial isn't free — we must add framing bits so the receiver can find where each byte starts (see 8b/10b Encoding). That costs a little efficiency:

Step 6 — The receiver must sample in the middle of each bit

WHAT. With no clock wire, the receiver rebuilds a clock from the incoming edges (PLL and Clock Synthesis powers this), then samples each bit. The safe place to sample is dead-centre, far from the wobbly edges.

WHY. Edges are where the signal is mid-transition — ambiguous. The centre is where the 1 is most clearly 1. The tolerance for how far the sampling clock may drift is exactly half a bit.

PICTURE. The stacked bit transitions form a diamond of open space called an eye diagram (Eye Diagrams). The green dot is the ideal sample point; the double arrow shows the $\pm T_{bit} /2$ you're allowed to drift before you fall out of the eye.

The one-picture summary

One figure, the whole argument: light crawls (Step 1) → unequal wires disagree by $Δ t_{skew}$ (Step 2) → the clock must wait for it plus setup/hold (Step 3) → at high speed skew eats the period (Step 4) → so we collapse to one serial lane where skew has no home (Step 5) → and recover the clock, sampling mid-eye (Step 6).

Recall Feynman retelling — say it like a friend

Picture a class where the teacher only reads homework at the exact bell. Parallel is 8 students walking in from 8 doors at different distances — the teacher must wait for the slowest one before reading, and that waiting is skew. Speed the bell up (faster clock) and the walking-in delay becomes a huge fraction of each bell interval — chaos. Serial says: forget 8 doors, have one super-fast runner sprint papers through a single door one at a time. There's no "slowest of eight" because there's only one. The catch: no separate bell wire, so the runner's own rhythm is the clock — the receiver watches the beat of arriving papers and reads each one right in the middle, never at the edge where it's mid-flip. That's the entire story of why the world went serial.

Recall Quick self-test

What physical fact makes skew unavoidable in parallel buses? ::: Signals travel at finite speed ( $v \approx 0.6 c$ ), so unequal trace lengths cause unequal arrival times. Write the parallel clock-period limit. ::: $T_{clk} \geq Δ t_{skew} + t_{setup} + t_{hold}$ . Why does serial have no inter-lane skew? ::: There is only one data lane, so there is no second wire to disagree with. How far may a CDR's sample point drift before errors? ::: Less than half a bit period, $∣Δ ϕ ∣ < T_{bit} /2$ . PCIe Gen3 per-lane usable rate? ::: $8.0 GT/s \times 128/130 \approx 7.88$ Gbps.