Serial vs parallel signaling (SerDes): Visual walkthrough

6.3.12 · D2 · Hardware › Interconnects, Buses & SoC › Serial vs Parallel Signaling (SerDes)

Yeh parent SerDes note ka visual companion hai. Pehle woh padho bade-picture callouts ke liye; yahan hum slow aur picture-first chalenge.

Step 1 — Ek bit ek voltage hai jo travel karne mein time leta hai

KYA HAI. "Skew" ya "bandwidth" ka koi matlab ban sake, usse pehle hume ek honest picture chahiye: ek single wire, aur ek voltage jo ya toh high (1) hai ya low (0). Yeh high/low pattern wire se wave ki tarah travel karta hai — yeh instant nahi hota.

KYUN. Parallel signaling ki har problem is ek fact se aati hai: bijli infinitely fast nahi hai. Agar yeh instant hota, toh saari wires perfectly agree karti aur yeh poora page blank hota. Toh hum yahan se shuru karte hain.

PICTURE. Neeche copper trace dekhein. Orange pulse ek 1 hai jo left-to-right move kar raha hai. Label $v$ uski speed hai.

Figure — Serial vs parallel signaling (SerDes)

Ek bit ko length $l$ ka trace cross karne mein jo time lagta hai woh sirf distance over speed hai:

$t_{fly} = \frac{l}{v}$

$l$ — copper trace kitni lambi hai (metres).
$v$ — upar se crawl speed.
$t_{fly}$ — "flight time", bit kitni der transit mein hai.

Step 2 — Do wires, do lengths → bits disagree karte hain

KYA HAI. Ab do wires side by side rakho aur ek-ek bit dono mein ek hi waqt bhejo. Agar wires alag-alag length ki hain, toh do bits alag-alag time pe pahunchti hain.

KYUN. Ek parallel bus bahut saari bits saath bhejti hai aur unhe ek clock tick se read karti hai. Yeh sirf tab kaam karta hai jab sab ek saath aayein. Toh jis pal do wires length mein alag hoti hain, hamare paas ek timing gap aa jaata hai — aur hume ise measure karna hoga.

PICTURE. Neeche, teal wire orange wire se thodi lambi hai. Launch time same hai, lekin lambi wali bit baad mein pahunchti hai. Dono landings ke beech ka gap is poore page ka star hai.

Step 3 — Clock ko sabse slow bit ka intezaar karna padta hai

KYA HAI. Receiver saari bits ko ek clock edge pe latch karta hai. Us latch ko correct values padhne ke liye, har bit ek chhoti si window mein edge ke aas-paas still (stable) rehni chahiye.

KYUN. Ek latch (flip-flop) bahut choosy hota hai. Isko data edge se pehle ek pal ke liye steady chahiye (ise $t_{setup}$ kehte hain) aur baad mein bhi ek pal ke liye (ise $t_{hold}$ kehte hain). Agar koi bit abhi bhi wobble kar rahi hai kyunki woh late pahunchi, toh read garbage hoga.

PICTURE. Green band woh "stable window" hai jo latch demand karta hai. Late (teal) bit slide karke andar aati hai aur safe time ko shrink kar deti hai. Notice karo kaise skew literally window ki start ko aage push kar deta hai.

Sab jodne pe, ek clock period itni lambi honi chahiye ki (a) skewed bits sab settle ho jayein, aur (b) setup + hold window ka samman ho:

Top speed padhne ke liye ise ulta karo. Ulta kyun? Frequency bas "ticks per second" hai, "seconds per tick" ka reciprocal:

$f_{m a x} = \frac{1}{T _{clk}} \leq \frac{1}{Δ t _{skew} + t _{setup} + t _{hold}}$

$f_{m a x}$ — bus sabse fast legally kitni clock kar sakti hai.
Jitna zyada $Δ t_{skew}$ hoga, utna chhhota $f_{m a x}$ hoga. Skew ek speed ceiling hai.

Step 4 — Real copper mein plug in karo: skew ek monster ban jaata hai

KYA HAI. Hum ek real-ish board ke liye $Δ t_{skew}$ calculate karte hain aur teen speeds pe clock period se compare karte hain.

KYUN. Ek formula abstract rehta hai jab tak tum percentages nahi dekhte. Poori "industry ne parallel kyun abandon kiya" ki kahani percentages ki ek table hai.

PICTURE. Bar chart mein clock period poora bar hai; orange chunk woh slice hai jo skew ne kha liya. Dekho orange slice bar ko kaise nigalta hai jab hum clock cranked karte hain.

Worked example 5 mm mismatch ke liye Skew

Length mismatch $Δ l = 5 mm = 5 \times 1 0^{- 3}$ m, speed $v = 1.8 \times 1 0^{8}$ m/s: $Δ t_{skew} = \frac{5 \times 1 0 ^{- 3}}{1.8 \times 1 0 ^{8}} \approx 2.78 \times 1 0^{- 11} s = 27.8 ps$ Ab teen speeds pe ek clock period $T = 1/ f$ se compare karo:

Clock $f$	Period $T$	Skew	Skew as $%$ of $T$
$133$ MHz	$7519$ ps	$27.8$ ps	$0.37%$ ✅
$1$ GHz	$1000$ ps	$27.8$ ps	$2.78%$ ⚠️
$5$ GHz	$200$ ps	$27.8$ ps	$13.9%$ ❌

Step 5 — Serial problem ko ek lane rakhke delete kar deta hai

KYA HAI. Serial signaling bits ko ek single differential pair (do wires jo same signal ki opposite copies carry karti hain) pe ek ke baad ek bhejta hai. Sirf ek data lane hone se, koi doosri wire nahi hai disagreement ke liye — inter-wire skew structurally khatam ho jaata hai.

KYUN. Agar sirf ek lane hai toh lanes ke beech length mismatch ho hi nahi sakta. Humne skew fix nahi kiya; humne uska ghar delete kar diya. (Dekhein Differential Signaling kyun pair noise ko bhi shrug off karta hai.)

PICTURE. Upar: 8 nervous parallel wires jo agree karni chahiye. Neeche: ek confident serial pair jo bits time mein stream kar raha hai. Clock ko uski apni wire pe bhejne ki jagah data edges se recover kiya jaata hai ek circuit se jise CDR kehte hain.

Lekin serial free nahi hai — hume framing bits add karni padti hain taaki receiver dhundh sake ki har byte kahan se shuru hoti hai (dekhein 8b/10b Encoding). Isse thodi efficiency ki cost hoti hai:

Step 6 — Receiver ko har bit ke middle mein sample karna hota hai

KYA HAI. Bina clock wire ke, receiver incoming edges se clock rebuild karta hai (PLL and Clock Synthesis yeh power karta hai), phir har bit sample karta hai. Sample karne ki safe jagah dead-centre hai, wobbly edges se door.

KYUN. Edges woh jagah hain jahan signal mid-transition mein hota hai — ambiguous. Centre woh jagah hai jahan 1 sabse clearly 1 hai. Sampling clock kitna drift kar sakti hai iske tolerance exactly aadha bit hai.

PICTURE. Stacked bit transitions ek khula diamond-shaped space banate hain jise eye diagram kehte hain (Eye Diagrams). Green dot ideal sample point hai; double arrow woh $\pm T_{bit} /2$ dikhata hai jo drift karne ki permission hai eye se bahar girne se pehle.

Ek-picture summary

Ek figure, poora argument: light crawls karti hai (Step 1) → unequal wires $Δ t_{skew}$ se disagree karti hain (Step 2) → clock ko uska aur setup/hold ka intezaar karna padta hai (Step 3) → high speed pe skew period kha jaata hai (Step 4) → toh hum ek serial lane pe collapse karte hain jahan skew ka ghar hi nahi hai (Step 5) → aur clock recover karte hain, mid-eye sample karte hue (Step 6).

Recall Feynman retelling — ek dost ki tarah bolo

Ek class imagine karo jahan teacher sirf exactly bell bajne pe homework read karti hai. Parallel mein 8 students 8 alag-alag doors se alag-alag dooriyon se andar aa rahe hain — teacher ko sabse slow wale ka wait karna padta hai padhne se pehle, aur woh waiting hi skew hai. Bell tez karo (faster clock) aur andar-aane ki delay har bell interval ka bada hissa ban jaati hai — chaos. Serial kehta hai: 8 doors bhool jao, ek super-fast runner bhejo jo ek door se ek ek karke papers sprint kare. "Aath mein se sabse slow" nahi hai kyunki hai hi sirf ek. Catch yeh hai: koi alag bell wire nahi, toh runner ki apni rhythm hi clock hai — receiver aane wale papers ki beat dekhta hai aur har ek ko theek beech mein read karta hai, kabhi edge pe nahi jahan woh mid-flip hota hai. Yahi poori kahani hai kyun duniya serial ho gayi.

Recall Quick self-test

Parallel buses mein skew ko unavoidable banane wala physical fact kya hai? ::: Signals finite speed pe travel karte hain ( $v \approx 0.6 c$ ), toh unequal trace lengths unequal arrival times cause karti hain. Parallel clock-period limit likho. ::: $T_{clk} \geq Δ t_{skew} + t_{setup} + t_{hold}$ . Serial mein inter-lane skew kyun nahi hota? ::: Sirf ek data lane hai, toh koi doosri wire hi nahi hai disagree karne ke liye. CDR ka sample point kitna drift kar sakta hai errors se pehle? ::: Aadhe bit period se kam, $∣Δ ϕ ∣ < T_{bit} /2$ . PCIe Gen3 per-lane usable rate? ::: $8.0 GT/s \times 128/130 \approx 7.88$ Gbps.