Serial vs parallel signaling (SerDes): Worked examples

This page is the "put a number on it" companion to the parent SerDes note. The parent gave you the formulas; here we hunt down every kind of question those formulas can produce and grind each one to a checkable number.

The scenario matrix

Every SerDes numeric question is really one of these situations. The columns are the quantity you solve for; the rows are the regime (which physical effect dominates or degenerates).

Regime → \ Solves for →	Skew / parallel limit	Serial data rate	Timing / CDR margin
Low speed (skew tiny)	Ex 1	—	—
High speed (skew fatal)	Ex 2	—	—
Degenerate / ideal (zero input)	Ex 3 (zero skew)	—	Ex 7 (zero drift)
Encoding overhead	—	Ex 4 (8b/10b), Ex 5 (128b/130b)	—
Multi-lane scaling	—	Ex 6 (x16)	—
Bit-period / sampling	—	—	Ex 8 (CDR budget)
Real-world word problem	Ex 9 (cable choice)	Ex 9	Ex 9
Exam twist (limiting value)	Ex 10 (crossover speed)	Ex 10	Ex 10

The two constants we reuse everywhere:

Here is the same map as a picture — which example sits in which regime:

Figure — Serial vs parallel signaling (SerDes)

Case: parallel skew regime

Ex 1 — Low speed, skew harmless (matrix: Low speed / skew limit)

Worked example A gentle 100 MHz parallel bus

A 32-bit parallel bus runs at $100 MHz$ . Worst-case trace-length mismatch between the shortest and longest data trace is $8 mm$ . What fraction of the clock period is lost to skew? Is the bus safe?

Forecast: guess now — is the skew under 1% of the period, or over 10%? (At only 100 MHz the period is long, so bet on "tiny".)

Convert length mismatch to time (skew). $Δ t_{s k e w} = \frac{l}{v} = \frac{8 \times 1 0 ^{- 3}}{1.8 \times 1 0 ^{8}} = 4.44 \times 1 0^{- 11} s = 44.4 ps$ Why this step? Skew is only a delay difference; the extra $8 mm$ of copper is what makes one bit arrive late. Delay = distance ÷ speed.
Find the clock period. $T_{c l k} = \frac{1}{100 \times 1 0 ^{6}} = 10 ns = 10000 ps$ Why this step? We judge skew relative to how long a bit is allowed to settle — the period.
Compute skew as a fraction. $\frac{44.4}{10000} = 0.00444 = 0.44%$ Why this step? A percentage is the only honest measure: 44 ps is meaningless until compared to the period.

Verify: 0.44% ≪ typical 15% danger threshold → safe. Units: ps/ps is dimensionless, correct. Sanity: slow clock ⇒ skew negligible, matches the parent's "at 1 GHz it's still fine" claim.

Ex 2 — High speed, skew fatal (matrix: High speed / skew limit)

Worked example The same wires at 6 GHz

Keep the $8 mm$ mismatch (skew $= 44.4 ps$ from Ex 1). Now push the parallel clock to $6 GHz$ . What fraction of the period is skew, and why does this force a switch to serial?

Forecast: The period shrank by 60×. Guess: does skew now exceed a quarter of the period?

New period. $T_{c l k} = \frac{1}{6 \times 1 0 ^{9}} = 1.667 \times 1 0^{- 10} s = 166.7 ps$ Why this step? Higher frequency = shorter period; the physical skew did not change, only the budget did.
Fraction lost. $\frac{44.4}{166.7} = 0.266 = 26.6%$ Why this step? Same skew, tiny period ⇒ skew now devours over a quarter of every bit window.

Verify: $26.6% > 15%$ danger line → the bus cannot sample reliably. This is exactly why designers move to a single differential serial lane where multi-wire alignment vanishes. Sanity: skew fraction from Ex 1 was 0.44%; multiplying frequency by 60 multiplies the fraction by 60 → $0.44% \times 60 = 26.6%$ . ✓

Ex 3 — Degenerate case: zero skew (matrix: Ideal / skew limit)

Worked example The impossible perfect PCB

Suppose a magical PCB makes all traces exactly equal length, so $Δ t_{s k e w} = 0$ . With $t_{se t u p} = 30 ps$ and $t_{h o l d} = 20 ps$ , what is the maximum parallel clock frequency?

Forecast: With zero skew, is the speed limit infinite, or does something else still cap it?

Recall the period floor (from the parent's skew formula): $T_{c l k} \geq Δ t_{s k e w} + t_{se t u p} + t_{h o l d}$ Why this step? Even with perfect traces, the flip-flop still needs setup + hold time to latch.
Substitute zero skew. $T_{c l k} \geq 0 + 30 + 20 = 50 ps$ Why this step? This is the degenerate input the matrix demands — it shows skew is not the only limit.
Invert for frequency. $f_{ma x} = \frac{1}{50 \times 1 0 ^{- 12}} = 2.0 \times 1 0^{10} Hz = 20 GHz$

Verify: Even the perfect bus caps at 20 GHz because of setup+hold. Units: $1/ s = Hz$ . ✓ Sanity: removing skew raised the limit but did not make it infinite — exactly the lesson of a degenerate-input check.

Case: serial data-rate regime

Ex 4 — 8b/10b encoding overhead (matrix: Encoding / data rate)

Ex 5 — Low-overhead 128b/130b (matrix: Encoding / data rate)

Ex 6 — Multi-lane scaling (matrix: Multi-lane / data rate)

Case: timing & CDR regime

Ex 7 — Degenerate case: zero frequency drift (matrix: Ideal / CDR)

Worked example Perfectly matched crystals

Transmitter and receiver share the exact same reference frequency, so the sampling clock never drifts. With ideal signaling, what phase error must the CDR correct, and does the link still need a CDR?

Forecast: Zero drift — is the CDR now useless?

Frequency offset is zero, so the accumulated timing error from drift is $0 ps$ . Why this step? Drift error grows as (frequency difference)×(time); with zero difference, it's flat zero.
But there is still no separate clock wire. The receiver must find mid-bit once at start-up. Why this step? This degenerate case shows the CDR's job splits into two: (a) track drift — now $0$ , and (b) find the initial sampling phase — still required.

Verify: Even with $0$ drift, the CDR is still needed to acquire phase; only the tracking load drops to zero. Sanity check against Ex 8: the drift budget there is what shrinks to nothing here.

Ex 8 — CDR sampling budget (matrix: Bit-period / CDR)

Ex 9 — Real-world word problem (matrix: word problem, spans all columns)

Worked example "Cable or PCB?" engineering decision

You must move $10 Gbps$ of user data between two chips $12 cm$ apart. Option A: a 16-bit parallel bus. Option B: a single serial lane at $12.5 Gbaud$ NRZ with 8b/10b. (a) Does Option B meet the 10 Gbps requirement? (b) For Option A, what per-wire skew results from a $6 mm$ mismatch, and what clock would 16 wires need?

Forecast: Bet on serial winning; guess whether the parallel clock lands in a comfortable or scary range.

Serial usable rate (Option B). $R_{d a t a} = 12.5 \times 1 0^{9} \times 0.8 \times 1 = 10.0 \times 1 0^{9} = 10.0 Gbps$ Why this step? Check the requirement directly with the data-rate engine; 8b/10b ⇒ $η = 0.8$ .
Serial verdict: $10.0 Gbps =$ requirement → meets it exactly on one differential pair.
Parallel skew (Option A). $Δ t_{s k e w} = \frac{6 \times 1 0 ^{- 3}}{1.8 \times 1 0 ^{8}} = 3.33 \times 1 0^{- 11} = 33.3 ps$ Why this step? Parallel's enemy is skew; convert the mismatch to time.
Parallel clock needed. 16 wires carrying 10 Gbps total need $10/16 = 0.625 Gbps per wire$ , i.e. $625 MHz$ , period $1600 ps$ . Skew fraction: $\frac{33.3}{1600} = 2.08%$ Why this step? We must confirm the skew is tolerable at the required clock.

Verify: Serial hits 10.0 Gbps on 2 wires; parallel hits it on 16 wires with 2.08% skew — technically fine but 8× the pin count and EMI. Choose serial (Option B). Units all consistent (ps/ps, Gbps). ✓

Ex 10 — Exam twist: the crossover speed (limiting value) (matrix: limiting value)

Worked example Where does parallel "die"?

Define parallel as unusable once skew reaches $25%$ of the clock period. For a bus with fixed skew $Δ t_{s k e w} = 40 ps$ , find the clock frequency at which parallel dies (the limiting value).

Forecast: Solve for the period where $40 ps$ is exactly a quarter of it, then invert. Guess the GHz.

Set the limiting condition. $\frac{Δ t _{s k e w}}{T _{c l k}} = 0.25 \Rightarrow T_{c l k} = \frac{Δ t _{s k e w}}{0.25} = \frac{40}{0.25} = 160 ps$ Why this step? "Dies at 25%" is an equation; solving it gives the exact period boundary — the limiting value the matrix wants.
Invert to frequency. $f_{d i e} = \frac{1}{160 \times 1 0 ^{- 12}} = 6.25 \times 1 0^{9} Hz = 6.25 GHz$ Why this step? Below 6.25 GHz parallel is fine; above it, this bus is dead — the crossover to serial.

Verify: Below $6.25 GHz$ → skew < 25% → OK; above → parallel unusable. Cross-check with Ex 2: at 6 GHz the 44.4 ps bus was at 26.6% (already dead), consistent since its skew exceeds 40 ps. ✓ Units: $1/ s = Hz$ . ✓

Recall Self-test — cover the answers

USB 3.0 at 5 Gbps: bit period? ::: $200 ps$ , so CDR window $= 100 ps$ . 8b/10b efficiency and its cost? ::: $η = 0.8$ ; you pay 20% overhead for DC balance + edges. PCIe Gen3 per-lane rate? ::: $8.0 \times \frac{128}{130} = 7.877 Gbps$ . Why doesn't zero skew give infinite parallel speed (Ex 3)? ::: setup + hold still floor the period (here 50 ps → 20 GHz). Crossover speed for a 40 ps-skew bus at the 25% rule? ::: $6.25 GHz$ .

See also: Equalization (CTLE, DFE) and PLL and Clock Synthesis for how real receivers widen the sampling window these examples assumed, and the DDR Memory Interface for the modern parallel bus that fights skew with per-bit training.