Exercises — Serial vs parallel signaling (SerDes)

• Serializer (transmitter): takes $n$ parallel bits sitting side-by-side on $n$ wires inside the chip and pushes them out one at a time on a single line — like feeding a stack of cards through one slot.
• Deserializer (receiver): watches that single stream of bits and rebuilds the original side-by-side group of $n$ bits.
• The Serializer lives at the transmitter (it serializes = makes serial before sending). See Serial vs parallel signaling (SerDes) for the block diagram.

The bit period is the reciprocal of the rate at which bits go by. Since each symbol is one bit here, the bit rate equals the symbol rate: $5\times 10^9$ bits per second. $T_{bit}=\frac{1}{R_s}=\frac{1}{5\times 10^9{\text{s}}^{-1}}=2\times 10^{-10}\text{s}=200\text{ps}$ Why reciprocal? If 5 billion bits pass every second, each bit gets $1/5,000,000,000$ of a second — dividing one second fairly among all the bits.

• (a) = Skew — a timing misalignment between wires.
• (b) = Crosstalk — capacitive/inductive coupling between an aggressor and a victim wire.
• (c) = EMI (electromagnetic interference) — the bus acting like an antenna. These are the three physics walls that pushed the industry from parallel to serial.

Skew is just extra distance divided by speed (time = distance / speed): $\Delta t_{skew}=\frac{\ell }{v}=\frac{8\times 10^{-3}\text{m}}{1.8\times 10^8\text{m/s}}=4.44\times 10^{-11}\text{s}\approx 44.4\text{ps}$ Why this formula? A wire that is 8 mm longer forces the signal to spend extra time crossing that extra copper. That delayed bit arrives late relative to its siblings — exactly the skew the receiver must tolerate.

First add up the minimum clock period. The clock cannot tick faster than the time needed for all bits to arrive (skew), settle (setup) and stay put (hold): $T_{clk,\min }=44.4+20+15=79.4\text{ps}=7.94\times 10^{-11}\text{s}$ The fastest clock is the reciprocal of the smallest allowed period: $f_{max}=\frac{1}{T_{clk,\min }}=\frac{1}{7.94\times 10^{-11}}\approx 1.26\times 10^{10}\text{Hz}\approx 12.6\text{GHz}$ Why an upper limit? Speed the clock past this and its period shrinks below $79.4$ ps — the clock edge arrives before every bit has settled, so the receiver samples garbage.

Use the note's formula $R_{data}=R_s\cdot \eta \cdot b$, where the efficiency $\eta$ is the fraction of transmitted bits that is real data: $\eta =\frac{128}{130}\approx 0.9846$ $R_{data}=8.0\times 10^9\times \frac{128}{130}\times 1\approx 7.877\times 10^9\text{bps}\approx 7.877\text{Gbps}$ Why multiply by $\eta <1$? Not every bit on the wire is your payload — 2 of every 130 are "packaging." You only get to keep the $128/130$ fraction. This matches 8b/10b Encoding logic, just with a leaner overhead. This is the per-lane rate of a PCIe Protocol Gen3 link.

Period $T=1/f$, then percentage $=\Delta t_{skew}/T\times 100\%$.

• 133 MHz: $T=1/(133\times 10^6)=7.52$ ns $=7519$ ps → $44.4/7519=0.59\%$. Trivial.
• 1 GHz: $T=1000$ ps → $44.4/1000=4.44\%$. Getting noticeable.
• 5 GHz: $T=200$ ps → $44.4/200=22.2\%$. Unmanageable — over one-fifth of the clock is eaten by skew alone. Analysis: the same physical mismatch is harmless at low speed and fatal at high speed, because the clock period shrinks while the skew (set by fixed board geometry) does not. In the figure, the red $5$ GHz bar towers over the dashed $10\%$ line — that is the physics wall that killed wide parallel buses. Serial dodges it by having one data lane, so there is no wire-to-wire alignment to lose.

Throughput now:

• Design A: $32\text{ bits}\times 400\times 10^6\text{ cycles/s}=1.28\times 10^{10}=12.8$ Gbps.
• Design B: $16\times 10^9\times 0.97\times 1=1.552\times 10^{10}=15.52$ Gbps.

Design B already wins ($15.52>12.8$ Gbps) on one lane vs 32 wires.

Scaling argument: To beat B, Design A must raise its 400 MHz clock. But its 32 wires each carry skew; as shown in 3.1, once the period drops near the skew, sampling fails. Design A hits the skew wall around a few GHz and pays with 32 pins of crosstalk and EMI. Design B has no wire-to-wire skew (one lane) and rejects noise as common-mode via Differential Signaling — so it keeps climbing (Gen4, Gen5...). Serial scales; wide parallel does not.

(a) A serializer sends all 8 bits during one slow-clock period, so it must shift 8 times as fast: $f_{high}=8\times f_{low}=8\times 1.25\times 10^9=1.0\times 10^{10}=10\text{GHz}$ (b) One bit per fast-clock cycle: $T_{bit}=\frac{1}{f_{high}}=\frac{1}{10\times 10^9}=1.0\times 10^{-10}\text{s}=100\text{ps}$ Check: 8 bits $\times$ 100 ps $=800$ ps $=1/(1.25\text{ GHz})$ — exactly one slow period. ✓ (c) 10110100, 100 ps per bit, MSB first, listed as (interval → bit → level):

• $0$–$100$ ps → bit $1$ → High
• $100$–$200$ ps → bit $0$ → Low
• $200$–$300$ ps → bit $1$ → High
• $300$–$400$ ps → bit $1$ → High
• $400$–$500$ ps → bit $0$ → Low
• $500$–$600$ ps → bit $1$ → High
• $600$–$700$ ps → bit $0$ → Low
• $700$–$800$ ps → bit $0$ → Low

Why the PLL? The chip's logic is comfortable at 1.25 GHz, but the wire must carry bits 8× faster. The PLL manufactures that 10 GHz clock by multiplying the slow one — it is the engine that lets one wire do the work of eight.

The safe window is the eye. To stay inside it, the sampling point may wander at most half the eye width from centre (drift left or right): $|\Delta \varphi {|}_{\max }=\frac{60\text{ps}}{2}=30\text{ps}$ A CDR locking to $\pm 8$ ps stays well inside: $8<30$. ✓ Succeeds with $22$ ps of margin. Why half the eye? Centre the sample in the eye for maximum safety. If it drifts more than half-way to either edge, it slips out of the open region and samples during a transition — a coin-flip bit. The parent note's rule $|\Delta \varphi |<T_{bit}/2$ is the idealised case (full-width eye); the eye diagram gives the real narrower budget after channel loss.

(a) Divide target by per-lane rate, round up (you cannot buy a fraction of a lane): $N_{lanes}=\lceil \frac{100\times 10^9}{7.877\times 10^9}\rceil =\lceil 12.7\rceil =13\text{lanes}$ Since PCIe link widths come in powers of two, you'd deploy an x16 link (16 lanes) in practice. (b) Each parallel wire gives $2.0\times 10^9=2$ Gbps: $N_{wires}=\lceil \frac{100\times 10^9}{2.0\times 10^9}\rceil =50\text{wires}$ (c) Physical wire count:

• Serial: $13$ lanes $\times 2$ wires $=26$ wires.
• Parallel: $50$ wires.

Serial wins ($26<50$), and it isn't even close once you add the parallel bus's clock/strobe wires. Deciding physics: each serial lane runs at $8$ GT/s cleanly because it's a lone differential pair with no wire-to-wire skew, low crosstalk, and cancelling EMI. The parallel bus is stuck at $2$ GHz precisely because 50 skewed, crosstalking, radiating wires cannot share a faster clock. Speed-per-wire, not wire-count, is what wins — the same lesson as DDR pushing per-pin rates rather than adding pins forever.

(a) A drift of $300$ ppm means the receiver's idea of the rate is off by a fraction $300/10^6=3\times 10^{-4}$: $\Delta R=R_s\times 300\times 10^{-6}=8.0\times 10^9\times 3\times 10^{-4}=2.4\times 10^6\text{symbols/s}=2.4\text{Msymbol/s}$ The receiver's clock counts $2.4$ million symbols per second more (or fewer) than the transmitter actually sends. (b) Because the two crystals never run at exactly the same frequency, a sampling point that is perfectly centred now will slide by $2.4$ million bit-widths every second if left alone — it would exit the eye in microseconds and every bit after that is wrong. So the CDR watches each incoming data edge, sees the phase creeping early or late, and nudges its local clock the opposite way, over and over. It is not a one-time alignment but a servo loop that tracks the transmitter's frequency for as long as the link is up — the exact behaviour the parent note describes for USB CDR.